C++ MachineBasicBlock::dump方法代码示例

void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
  this->MBB = &MBB;
  LLVM_DEBUG(dbgs() << "\nAllocating " << MBB);

  PhysRegState.assign(TRI->getNumRegs(), regDisabled);
  assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?");

  MachineBasicBlock::iterator MII = MBB.begin();

  // Add live-in registers as live.
  for (const MachineBasicBlock::RegisterMaskPair LI : MBB.liveins())
    if (MRI->isAllocatable(LI.PhysReg))
      definePhysReg(MII, LI.PhysReg, regReserved);

  VirtDead.clear();
  Coalesced.clear();

  // Otherwise, sequentially allocate each instruction in the MBB.
  for (MachineInstr &MI : MBB) {
    LLVM_DEBUG(
      dbgs() << "\n>> " << MI << "Regs:";
      dumpState()
    );

    // Special handling for debug values. Note that they are not allowed to
    // affect codegen of the other instructions in any way.
    if (MI.isDebugValue()) {
      handleDebugValue(MI);
      continue;
    }

    allocateInstruction(MI);
  }

  // Spill all physical registers holding virtual registers now.
  LLVM_DEBUG(dbgs() << "Spilling live registers at end of block.\n");
  spillAll(MBB.getFirstTerminator());

  // Erase all the coalesced copies. We are delaying it until now because
  // LiveVirtRegs might refer to the instrs.
  for (MachineInstr *MI : Coalesced)
    MBB.erase(MI);
  NumCoalesced += Coalesced.size();

  LLVM_DEBUG(MBB.dump());
}

unsigned LM32InstrInfo::
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
             MachineBasicBlock *FBB,
             const SmallVectorImpl<MachineOperand> &Cond,
             DebugLoc DL) const {
  // Shouldn't be a fall through.
  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
  assert((Cond.size() == 2 || Cond.size() == 0) &&
         "LM32 branch conditions have two components!");

  unsigned Opc = LM32::BI;
  if (!Cond.empty())
    Opc = (unsigned)Cond[0].getImm();

  DEBUG(dbgs() << "InsertBranch:Opcode:  " << Opc << "\n");
  DEBUG(dbgs() << "InsertBranch: MBB:    " << MBB.getName().str() << "\n");
  DEBUG(dbgs() << "InsertBranch: MBB:    " << MBB << "\n");
  DEBUG( MBB.dump(););

/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
/// under the assuption that it needs to be lowered in a way that supports
/// atomic execution of PHIs.  This lowering method is always correct all of the
/// time.
///
void PHIElimination::LowerAtomicPHINode(
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator AfterPHIsIt) {
  ++NumAtomic;
  // Unlink the PHI node from the basic block, but don't delete the PHI yet.
  MachineInstr *MPhi = MBB.remove(MBB.begin());

  unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
  unsigned DestReg = MPhi->getOperand(0).getReg();
  assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
  bool isDead = MPhi->getOperand(0).isDead();

  // Create a new register for the incoming PHI arguments.
  MachineFunction &MF = *MBB.getParent();
  unsigned IncomingReg = 0;
  bool reusedIncoming = false;  // Is IncomingReg reused from an earlier PHI?

  // Insert a register to register copy at the top of the current block (but
  // after any remaining phi nodes) which copies the new incoming register
  // into the phi node destination.
  const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
  if (isSourceDefinedByImplicitDef(MPhi, MRI))
    // If all sources of a PHI node are implicit_def, just emit an
    // implicit_def instead of a copy.
    BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
            TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
  else {
    // Can we reuse an earlier PHI node? This only happens for critical edges,
    // typically those created by tail duplication.
    unsigned &entry = LoweredPHIs[MPhi];
    if (entry) {
      // An identical PHI node was already lowered. Reuse the incoming register.
      IncomingReg = entry;
      reusedIncoming = true;
      ++NumReused;
      DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
    } else {
      const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
      entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
    }
    BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
            TII->get(TargetOpcode::COPY), DestReg)
      .addReg(IncomingReg);
  }

  // Update live variable information if there is any.
  LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
  if (LV) {
    MachineInstr *PHICopy = prior(AfterPHIsIt);

    if (IncomingReg) {
      LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);

      // Increment use count of the newly created virtual register.
      VI.NumUses++;
      LV->setPHIJoin(IncomingReg);

      // When we are reusing the incoming register, it may already have been
      // killed in this block. The old kill will also have been inserted at
      // AfterPHIsIt, so it appears before the current PHICopy.
      if (reusedIncoming)
        if (MachineInstr *OldKill = VI.findKill(&MBB)) {
          DEBUG(dbgs() << "Remove old kill from " << *OldKill);
          LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
          DEBUG(MBB.dump());
        }

      // Add information to LiveVariables to know that the incoming value is
      // killed.  Note that because the value is defined in several places (once
      // each for each incoming block), the "def" block and instruction fields
      // for the VarInfo is not filled in.
      LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
    }

    // Since we are going to be deleting the PHI node, if it is the last use of
    // any registers, or if the value itself is dead, we need to move this
    // information over to the new copy we just inserted.
    LV->removeVirtualRegistersKilled(MPhi);

    // If the result is dead, update LV.
    if (isDead) {
      LV->addVirtualRegisterDead(DestReg, PHICopy);
      LV->removeVirtualRegisterDead(DestReg, MPhi);
    }
  }

  // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
  for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
    --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
                                 MPhi->getOperand(i).getReg())];

  // Now loop over all of the incoming arguments, changing them to copy into the
  // IncomingReg register in the corresponding predecessor basic block.
  SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
  for (int i = NumSrcs - 1; i >= 0; --i) {
//.........这里部分代码省略.........

/// LowerPHINode - Lower the PHI node at the top of the specified block,
///
void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator LastPHIIt) {
    ++NumLowered;

    MachineBasicBlock::iterator AfterPHIsIt = llvm::next(LastPHIIt);

    // Unlink the PHI node from the basic block, but don't delete the PHI yet.
    MachineInstr *MPhi = MBB.remove(MBB.begin());

    unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
    unsigned DestReg = MPhi->getOperand(0).getReg();
    assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
    bool isDead = MPhi->getOperand(0).isDead();

    // Create a new register for the incoming PHI arguments.
    MachineFunction &MF = *MBB.getParent();
    unsigned IncomingReg = 0;
    bool reusedIncoming = false;  // Is IncomingReg reused from an earlier PHI?

    // Insert a register to register copy at the top of the current block (but
    // after any remaining phi nodes) which copies the new incoming register
    // into the phi node destination.
    const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
    if (isSourceDefinedByImplicitDef(MPhi, MRI))
        // If all sources of a PHI node are implicit_def, just emit an
        // implicit_def instead of a copy.
        BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
                TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
    else {
        // Can we reuse an earlier PHI node? This only happens for critical edges,
        // typically those created by tail duplication.
        unsigned &entry = LoweredPHIs[MPhi];
        if (entry) {
            // An identical PHI node was already lowered. Reuse the incoming register.
            IncomingReg = entry;
            reusedIncoming = true;
            ++NumReused;
            DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
        } else {
            const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
            entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
        }
        BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
                TII->get(TargetOpcode::COPY), DestReg)
        .addReg(IncomingReg);
    }

    // Update live variable information if there is any.
    if (LV) {
        MachineInstr *PHICopy = prior(AfterPHIsIt);

        if (IncomingReg) {
            LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);

            // Increment use count of the newly created virtual register.
            LV->setPHIJoin(IncomingReg);

            // When we are reusing the incoming register, it may already have been
            // killed in this block. The old kill will also have been inserted at
            // AfterPHIsIt, so it appears before the current PHICopy.
            if (reusedIncoming)
                if (MachineInstr *OldKill = VI.findKill(&MBB)) {
                    DEBUG(dbgs() << "Remove old kill from " << *OldKill);
                    LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
                    DEBUG(MBB.dump());
                }

            // Add information to LiveVariables to know that the incoming value is
            // killed.  Note that because the value is defined in several places (once
            // each for each incoming block), the "def" block and instruction fields
            // for the VarInfo is not filled in.
            LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
        }

        // Since we are going to be deleting the PHI node, if it is the last use of
        // any registers, or if the value itself is dead, we need to move this
        // information over to the new copy we just inserted.
        LV->removeVirtualRegistersKilled(MPhi);

        // If the result is dead, update LV.
        if (isDead) {
            LV->addVirtualRegisterDead(DestReg, PHICopy);
            LV->removeVirtualRegisterDead(DestReg, MPhi);
        }
    }

    // Update LiveIntervals for the new copy or implicit def.
    if (LIS) {
        MachineInstr *NewInstr = prior(AfterPHIsIt);
        SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);

        SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
        if (IncomingReg) {
            // Add the region from the beginning of MBB to the copy instruction to
            // IncomingReg's live interval.
            LiveInterval &IncomingLI = LIS->getOrCreateInterval(IncomingReg);
            VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
            if (!IncomingVNI)
//.........这里部分代码省略.........

/// Splits a MachineBasicBlock to branch before \p SplitBefore. The original
/// branch is \p OrigBranch. The target of the new branch can either be the same
/// as the target of the original branch or the fallthrough successor of the
/// original block as determined by \p BranchToFallThrough. The branch
/// conditions will be inverted according to \p InvertNewBranch and
/// \p InvertOrigBranch. If an instruction that previously fed the branch is to
/// be deleted, it is provided in \p MIToDelete and \p NewCond will be used as
/// the branch condition. The branch probabilities will be set if the
/// MachineBranchProbabilityInfo isn't null.
static bool splitMBB(BlockSplitInfo &BSI) {
  assert(BSI.allInstrsInSameMBB() &&
         "All instructions must be in the same block.");

  MachineBasicBlock *ThisMBB = BSI.OrigBranch->getParent();
  MachineFunction *MF = ThisMBB->getParent();
  MachineRegisterInfo *MRI = &MF->getRegInfo();
  assert(MRI->isSSA() && "Can only do this while the function is in SSA form.");
  if (ThisMBB->succ_size() != 2) {
    LLVM_DEBUG(
        dbgs() << "Don't know how to handle blocks that don't have exactly"
               << " two successors.\n");
    return false;
  }

  const PPCInstrInfo *TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
  unsigned OrigBROpcode = BSI.OrigBranch->getOpcode();
  unsigned InvertedOpcode =
      OrigBROpcode == PPC::BC
          ? PPC::BCn
          : OrigBROpcode == PPC::BCn
                ? PPC::BC
                : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR;
  unsigned NewBROpcode = BSI.InvertNewBranch ? InvertedOpcode : OrigBROpcode;
  MachineBasicBlock *OrigTarget = BSI.OrigBranch->getOperand(1).getMBB();
  MachineBasicBlock *OrigFallThrough = OrigTarget == *ThisMBB->succ_begin()
                                           ? *ThisMBB->succ_rbegin()
                                           : *ThisMBB->succ_begin();
  MachineBasicBlock *NewBRTarget =
      BSI.BranchToFallThrough ? OrigFallThrough : OrigTarget;
  BranchProbability ProbToNewTarget =
      !BSI.MBPI ? BranchProbability::getUnknown()
                : BSI.MBPI->getEdgeProbability(ThisMBB, NewBRTarget);

  // Create a new basic block.
  MachineBasicBlock::iterator InsertPoint = BSI.SplitBefore;
  const BasicBlock *LLVM_BB = ThisMBB->getBasicBlock();
  MachineFunction::iterator It = ThisMBB->getIterator();
  MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(LLVM_BB);
  MF->insert(++It, NewMBB);

  // Move everything after SplitBefore into the new block.
  NewMBB->splice(NewMBB->end(), ThisMBB, InsertPoint, ThisMBB->end());
  NewMBB->transferSuccessors(ThisMBB);

  // Add the two successors to ThisMBB. The probabilities come from the
  // existing blocks if available.
  ThisMBB->addSuccessor(NewBRTarget, ProbToNewTarget);
  ThisMBB->addSuccessor(NewMBB, ProbToNewTarget.getCompl());

  // Add the branches to ThisMBB.
  BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
          TII->get(NewBROpcode))
      .addReg(BSI.SplitCond->getOperand(0).getReg())
      .addMBB(NewBRTarget);
  BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
          TII->get(PPC::B))
      .addMBB(NewMBB);
  if (BSI.MIToDelete)
    BSI.MIToDelete->eraseFromParent();

  // Change the condition on the original branch and invert it if requested.
  auto FirstTerminator = NewMBB->getFirstTerminator();
  if (BSI.NewCond) {
    assert(FirstTerminator->getOperand(0).isReg() &&
           "Can't update condition of unconditional branch.");
    FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());
  }
  if (BSI.InvertOrigBranch)
    FirstTerminator->setDesc(TII->get(InvertedOpcode));

  // If any of the PHIs in the successors of NewMBB reference values that
  // now come from NewMBB, they need to be updated.
  for (auto *Succ : NewMBB->successors()) {
    updatePHIs(Succ, ThisMBB, NewMBB, MRI);
  }
  addIncomingValuesToPHIs(NewBRTarget, ThisMBB, NewMBB, MRI);

  LLVM_DEBUG(dbgs() << "After splitting, ThisMBB:\n"; ThisMBB->dump());
  LLVM_DEBUG(dbgs() << "NewMBB:\n"; NewMBB->dump());
  LLVM_DEBUG(dbgs() << "New branch-to block:\n"; NewBRTarget->dump());
  return true;
}

bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {

  DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
               << "********** Function: "
               << MF.getName() << "\n");

  if (skipFunction(*MF.getFunction()))
    return false;

  // If we move NewValueJump before register allocation we'll need live variable
  // analysis here too.

  QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
  QRI = static_cast<const HexagonRegisterInfo *>(
      MF.getSubtarget().getRegisterInfo());
  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();

  if (DisableNewValueJumps) {
    return false;
  }

  int nvjCount = DbgNVJCount;
  int nvjGenerated = 0;

  // Loop through all the bb's of the function
  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
        MBBb != MBBe; ++MBBb) {
    MachineBasicBlock *MBB = &*MBBb;

    DEBUG(dbgs() << "** dumping bb ** "
                 << MBB->getNumber() << "\n");
    DEBUG(MBB->dump());
    DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
    bool foundJump    = false;
    bool foundCompare = false;
    bool invertPredicate = false;
    unsigned predReg = 0; // predicate reg of the jump.
    unsigned cmpReg1 = 0;
    int cmpOp2 = 0;
    bool MO1IsKill = false;
    bool MO2IsKill = false;
    MachineBasicBlock::iterator jmpPos;
    MachineBasicBlock::iterator cmpPos;
    MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
    MachineBasicBlock *jmpTarget = nullptr;
    bool afterRA = false;
    bool isSecondOpReg = false;
    bool isSecondOpNewified = false;
    // Traverse the basic block - bottom up
    for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
             MII != E;) {
      MachineInstr &MI = *--MII;
      if (MI.isDebugValue()) {
        continue;
      }

      if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
        break;

      DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");

      if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
                         MI.getOpcode() == Hexagon::J2_jumpf ||
                         MI.getOpcode() == Hexagon::J2_jumptnewpt ||
                         MI.getOpcode() == Hexagon::J2_jumptnew ||
                         MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
                         MI.getOpcode() == Hexagon::J2_jumpfnew)) {
        // This is where you would insert your compare and
        // instr that feeds compare
        jmpPos = MII;
        jmpInstr = &MI;
        predReg = MI.getOperand(0).getReg();
        afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);

        // If ifconverter had not messed up with the kill flags of the
        // operands, the following check on the kill flag would suffice.
        // if(!jmpInstr->getOperand(0).isKill()) break;

        // This predicate register is live out out of BB
        // this would only work if we can actually use Live
        // variable analysis on phy regs - but LLVM does not
        // provide LV analysis on phys regs.
        //if(LVs.isLiveOut(predReg, *MBB)) break;

        // Get all the successors of this block - which will always
        // be 2. Check if the predicate register is live in in those
        // successor. If yes, we can not delete the predicate -
        // I am doing this only because LLVM does not provide LiveOut
        // at the BB level.
        bool predLive = false;
        for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
                            SIE = MBB->succ_end(); SI != SIE; ++SI) {
          MachineBasicBlock* succMBB = *SI;
         if (succMBB->isLiveIn(predReg)) {
            predLive = true;
          }
        }
        if (predLive)
          break;

//.........这里部分代码省略.........

// AnalyzeBranch returns a Boolean value and takes four parameters:
//    MachineBasicBlock &MBB — The incoming block to be examined.
//    MachineBasicBlock *&TBB — A destination block that is returned. For
//         a conditional branch that evaluates to true, TBB is the destination.
//    MachineBasicBlock *&FBB — For a conditional branch that evaluates to
//         false, FBB is returned as the destination.
//    std::vector<MachineOperand> &Cond — List of operands to evaluate a
//         condition for a conditional branch.
//  Return false if the branch is sucessfully analyzed, true otherwise.
//
//  Note that Cond appears to be  only used by the target specific code.  The
//  generic code just checks if Cond is empty or not.
bool LM32InstrInfo::
AnalyzeBranch(MachineBasicBlock &MBB,
              MachineBasicBlock *&TBB,
              MachineBasicBlock *&FBB,
              SmallVectorImpl<MachineOperand> &Cond,
              bool AllowModify) const
{
// The Cond parameters need to be fixed - disable this for now.
return true;
    DEBUG(dbgs() << "AnalyzeBranch: blocks:\n");
    DEBUG(MBB.dump());
    DEBUG(dbgs() << "AnalyzeBranch: end blocks:\n");

  // If the block has no terminators, it just falls into the block after it.

  MachineBasicBlock::iterator I = MBB.end();
  if (I == MBB.begin())
    return false;
  --I;
  while (I->isDebugValue()) {
    if (I == MBB.begin())
      return false;
    --I;
  }
  if (!isUnpredicatedTerminator(I)) {
    DEBUG(dbgs() << "AnalyzeBranch:predicated Terminator\n");
    DEBUG(dbgs() << "AnalyzeBranch: MBB:    " << MBB.getName().str() << "\n");
    return false;
  }

  // Get the last instruction in the block.
  MachineInstr *LastInst = I;

  // If there is only one terminator instruction, process it.
  unsigned LastOpc = LastInst->getOpcode();
  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
    if (LM32::isUncondBranchOpcode(LastOpc)) {
  DEBUG(dbgs() << "AnalyzeBranch:one terminator instruction\n");
      TBB = LastInst->getOperand(0).getMBB();
  DEBUG(dbgs() << "AnalyzeBranch: instruction: " << *LastInst << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: opcode: " << LastInst->getOpcode() << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: MBB:    " << MBB.getName().str() << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: TBB:    " << TBB->getName().str() << "\n");

      return false;
    }
    if (LM32::isCondBranchOpcode(LastOpc)) {
      // Block ends with fall-through condbranch.
  DEBUG(dbgs() << "AnalyzeBranch:Block ends with fall-through condbranch\n");
  DEBUG(dbgs() << "AnalyzeBranch: instruction: " << *LastInst << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: opcode: " << LastOpc << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: MBB:    " << MBB.getName().str() << "\n");
      TBB = GetBranchTarget(*LastInst);
      Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
      Cond.push_back(LastInst->getOperand(0));
  DEBUG(dbgs() << "AnalyzeBranch: TBB:    " << TBB->getName().str() << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: Cond[0]:" << Cond[0] << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: Cond[1]:" << Cond[1] << "\n");

      return false;
    }
    // Otherwise, don't know what this is.
    return true;
  }

  // Get the instruction before it if it's a terminator.
  MachineInstr *SecondLastInst = I;

  // If there are three terminators, we don't know what sort of block this is.
  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
    return true;

  // The block ends with both a conditional branch and an ensuing
  // unconditional branch. 
  if (LM32::isCondBranchOpcode(SecondLastInst->getOpcode()) &&
      LM32::isUncondBranchOpcode(LastInst->getOpcode())) {
  DEBUG(dbgs() << "AnalyzeBranch:Conditional branch and ensuing unconditional\n");
    TBB = GetBranchTarget(*SecondLastInst);
    Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
    Cond.push_back(SecondLastInst->getOperand(0));
    FBB = GetBranchTarget(*LastInst);
  DEBUG(dbgs() << "AnalyzeBranch: 2nd instr:   " << *SecondLastInst << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: last instr:  " << *LastInst << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: 2nd opcode:  " << SecondLastInst->getOpcode() << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: last opcode: " << LastInst->getOpcode() << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: MBB:    " << MBB.getName().str() << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: TBB:    " << TBB->getName().str() << "\n");
  DEBUG(dbgs() << "AnalyzeBranch: FBB:    " << FBB->getName().str() << "\n");
//.........这里部分代码省略.........