本文整理汇总了C++中TRACK::Type方法的典型用法代码示例。如果您正苦于以下问题:C++ TRACK::Type方法的具体用法?C++ TRACK::Type怎么用?C++ TRACK::Type使用的例子?那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类TRACK
的用法示例。
在下文中一共展示了TRACK::Type方法的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: Abort_Create_Track
/* Function called to abort a track creation
*/
static void Abort_Create_Track( EDA_DRAW_PANEL* Panel, wxDC* DC )
{
PCB_EDIT_FRAME* frame = (PCB_EDIT_FRAME*) Panel->GetParent();
BOARD* pcb = frame->GetBoard();
TRACK* track = (TRACK*) frame->GetCurItem();
if( track && ( track->Type()==PCB_VIA_T || track->Type()==PCB_TRACE_T ) )
{
// Erase the current drawing
ShowNewTrackWhenMovingCursor( Panel, DC, wxDefaultPosition, false );
if( pcb->IsHighLightNetON() )
frame->HighLight( DC );
pcb->PopHighLight();
if( pcb->IsHighLightNetON() )
pcb->DrawHighLight( Panel, DC, pcb->GetHighLightNetCode() );
frame->ClearMsgPanel();
// Undo pending changes (mainly a lock point creation) and clear the
// undo picker list:
frame->PutDataInPreviousState( &s_ItemsListPicker, false, false );
s_ItemsListPicker.ClearListAndDeleteItems();
// Delete current (new) track
g_CurrentTrackList.DeleteAll();
}
frame->SetCurItem( NULL );
}
示例2: testKeepoutAreas
void DRC::testKeepoutAreas()
{
// Test keepout areas for vias, tracks and pads inside keepout areas
for( int ii = 0; ii < m_pcb->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* area = m_pcb->GetArea( ii );
if( !area->GetIsKeepout() )
continue;
for( TRACK* segm = m_pcb->m_Track; segm != NULL; segm = segm->Next() )
{
if( segm->Type() == PCB_TRACE_T )
{
if( ! area->GetDoNotAllowTracks() )
continue;
if( segm->GetLayer() != area->GetLayer() )
continue;
if( area->Outline()->Distance( segm->GetStart(), segm->GetEnd(),
segm->GetWidth() ) == 0 )
{
m_currentMarker = fillMarker( segm, NULL,
DRCE_TRACK_INSIDE_KEEPOUT, m_currentMarker );
m_pcb->Add( m_currentMarker );
m_mainWindow->GetGalCanvas()->GetView()->Add( m_currentMarker );
m_currentMarker = 0;
}
}
else if( segm->Type() == PCB_VIA_T )
{
if( ! area->GetDoNotAllowVias() )
continue;
if( ! ((VIA*)segm)->IsOnLayer( area->GetLayer() ) )
continue;
if( area->Outline()->Distance( segm->GetPosition() ) < segm->GetWidth()/2 )
{
m_currentMarker = fillMarker( segm, NULL,
DRCE_VIA_INSIDE_KEEPOUT, m_currentMarker );
m_pcb->Add( m_currentMarker );
m_mainWindow->GetGalCanvas()->GetView()->Add( m_currentMarker );
m_currentMarker = 0;
}
}
}
// Test pads: TODO
}
}
示例3: clean_segments
// Delete null length segments, and intermediate points ..
bool TRACKS_CLEANER::clean_segments()
{
bool modified = false;
// Easy things first
modified |= delete_null_segments();
// Delete redundant segments, i.e. segments having the same end points and layers
for( TRACK *segment = m_Brd->m_Track; segment; segment = segment->Next() )
modified |= remove_duplicates_of_track( segment );
// merge collinear segments:
TRACK *nextsegment;
for( TRACK *segment = m_Brd->m_Track; segment; segment = nextsegment )
{
nextsegment = segment->Next();
if( segment->Type() == PCB_TRACE_T )
{
bool merged_this = merge_collinear_of_track( segment );
modified |= merged_this;
if( merged_this ) // The current segment was modified, retry to merge it again
nextsegment = segment->Next();
}
}
return modified;
}
示例4: remove_duplicates_of_track
bool TRACKS_CLEANER::remove_duplicates_of_track( const TRACK *aTrack )
{
bool modified = false;
TRACK *nextsegment;
for( TRACK *other = aTrack->Next(); other; other = nextsegment )
{
nextsegment = other->Next();
// New netcode, break out (can't be there any other)
if( aTrack->GetNetCode() != other->GetNetCode() )
break;
// Must be of the same type, on the same layer and the endpoints
// must be the same (maybe swapped)
if( (aTrack->Type() != other->Type()) &&
(aTrack->GetLayer() != other->GetLayer()) )
{
if( ((aTrack->GetStart() == other->GetStart()) &&
(aTrack->GetEnd() == other->GetEnd())) ||
((aTrack->GetStart() == other->GetEnd()) &&
(aTrack->GetEnd() == other->GetStart())))
{
m_Brd->GetRatsnest()->Remove( other );
other->ViewRelease();
other->DeleteStructure();
modified = true;
}
}
}
return modified;
}
示例5: Swap_Layers
void PCB_EDIT_FRAME::Swap_Layers( wxCommandEvent& event )
{
PCB_LAYER_ID new_layer[PCB_LAYER_ID_COUNT];
DIALOG_SWAP_LAYERS dlg( this, new_layer );
if( dlg.ShowModal() != wxID_OK )
return;
BOARD_COMMIT commit( this );
bool hasChanges = false;
// Change tracks.
for( TRACK* segm = GetBoard()->m_Track; segm; segm = segm->Next() )
{
if( segm->Type() == PCB_VIA_T )
{
VIA* via = (VIA*) segm;
PCB_LAYER_ID top_layer, bottom_layer;
if( via->GetViaType() == VIA_THROUGH )
continue;
via->LayerPair( &top_layer, &bottom_layer );
if( new_layer[bottom_layer] != bottom_layer || new_layer[top_layer] != top_layer )
{
commit.Modify( via );
via->SetLayerPair( new_layer[top_layer], new_layer[bottom_layer] );
GetGalCanvas()->GetView()->Update( via, KIGFX::GEOMETRY );
hasChanges = true;
}
}
else
{
hasChanges |= processBoardItem( this, commit, segm, new_layer );
}
}
for( BOARD_ITEM* zone : GetBoard()->Zones() )
{
hasChanges |= processBoardItem( this, commit, zone, new_layer );
}
for( BOARD_ITEM* drawing : GetBoard()->Drawings() )
{
hasChanges |= processBoardItem( this, commit, drawing, new_layer );
}
if( hasChanges )
{
OnModify();
commit.Push( "Layers moved" );
GetCanvas()->Refresh();
}
}
示例6: export_vrml_tracks
static void export_vrml_tracks( BOARD* pcb ) //{{{
{
for( TRACK* track = pcb->m_Track; track != NULL; track = track->Next() )
{
if( track->Type() == PCB_VIA_T )
export_vrml_via( pcb, (SEGVIA*) track );
else
export_vrml_line( track->GetLayer(), track->GetStart().x, track->GetStart().y,
track->GetEnd().x, track->GetEnd().y, track->GetWidth(), 4 );
}
}
示例7: Show_MoveNode
// Redraw the moved node according to the mouse cursor position
static void Show_MoveNode( EDA_DRAW_PANEL* aPanel, wxDC* aDC, const wxPoint& aPosition,
bool aErase )
{
auto displ_opts = (PCB_DISPLAY_OPTIONS*) aPanel->GetDisplayOptions();
wxPoint moveVector;
int tmp = displ_opts->m_DisplayPcbTrackFill;
GR_DRAWMODE draw_mode = GR_XOR | GR_HIGHLIGHT;
displ_opts->m_DisplayPcbTrackFill = false;
#ifndef USE_WX_OVERLAY
aErase = true;
#else
aErase = false;
#endif
// set the new track coordinates
wxPoint Pos = aPanel->GetParent()->GetCrossHairPosition();
moveVector = Pos - s_LastPos;
s_LastPos = Pos;
TRACK *track = NULL;
for( unsigned ii = 0; ii < g_DragSegmentList.size(); ii++ )
{
track = g_DragSegmentList[ii].m_Track;
if( aErase )
track->Draw( aPanel, aDC, draw_mode );
if( track->GetFlags() & STARTPOINT )
track->SetStart( track->GetStart() + moveVector );
if( track->GetFlags() & ENDPOINT )
track->SetEnd( track->GetEnd() + moveVector );
if( track->Type() == PCB_VIA_T )
track->SetEnd( track->GetStart() );
track->Draw( aPanel, aDC, draw_mode );
}
displ_opts->m_DisplayPcbTrackFill = tmp;
// Display track length
if( track )
{
PCB_BASE_FRAME* frame = (PCB_BASE_FRAME*) aPanel->GetParent();
frame->SetMsgPanel( track );
}
}
示例8: merge_collinear_of_track
bool TRACKS_CLEANER::merge_collinear_of_track( TRACK *aSegment )
{
bool merged_this = false;
// *WHY* doesn't C++ have prec and succ (or ++ --) like PASCAL?
for( ENDPOINT_T endpoint = ENDPOINT_START; endpoint <= ENDPOINT_END;
endpoint = ENDPOINT_T( endpoint + 1 ) )
{
// search for a possible segment connected to the current endpoint of the current one
TRACK *other = aSegment->Next();
if( other )
{
other = aSegment->GetTrack( other, NULL, endpoint, true, false );
if( other )
{
// the two segments must have the same width and the other
// cannot be a via
if( (aSegment->GetWidth() == other->GetWidth()) &&
(other->Type() == PCB_TRACE_T) )
{
// There can be only one segment connected
other->SetState( BUSY, true );
TRACK *yet_another = aSegment->GetTrack( m_Brd->m_Track, NULL,
endpoint, true, false );
other->SetState( BUSY, false );
if( !yet_another )
{
// Try to merge them
TRACK *segDelete = mergeCollinearSegmentIfPossible( aSegment,
other, endpoint );
// Merge succesful, the other one has to go away
if( segDelete )
{
m_Brd->GetRatsnest()->Remove( segDelete );
segDelete->ViewRelease();
segDelete->DeleteStructure();
merged_this = true;
}
}
}
}
}
}
return merged_this;
}
示例9: SyncWorld
void PNS_ROUTER::SyncWorld()
{
if( !m_board )
{
TRACEn( 0, "No board attached, aborting sync." );
return;
}
ClearWorld();
m_world = new PNS_NODE();
for( MODULE* module = m_board->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
{
PNS_ITEM* solid = syncPad( pad );
if( solid )
m_world->Add( solid );
}
}
for( TRACK* t = m_board->m_Track; t; t = t->Next() )
{
KICAD_T type = t->Type();
PNS_ITEM* item = NULL;
if( type == PCB_TRACE_T )
item = syncTrack( t );
else if( type == PCB_VIA_T )
item = syncVia( static_cast<VIA*>( t ) );
if( item )
m_world->Add( item );
}
// TODO: Create resolvers in ctor, call resolver->SetBoard() in this->SetBoard() and delete it in dtor
// TBD: Same remark as with m_sizes.SetMinimumTrackWidth in startRouting()
int worstClearance = m_board->GetDesignSettings().GetBiggestClearanceValue();
m_clearanceResolver = new PNS_PCBNEW_CLEARANCE_RESOLVER( this );
m_world->SetClearanceResolver( m_clearanceResolver );
m_world->SetMaxClearance( 4 * worstClearance );
m_pairingResolver = new PCBNEW_PAIRING_RESOLVER( m_board );
m_world->SetPairingResolver( m_pairingResolver );
}
示例10: export_vrml_tracks
static void export_vrml_tracks( MODEL_VRML& aModel, BOARD* pcb )
{
for( TRACK* track = pcb->m_Track; track; track = track->Next() )
{
if( track->Type() == PCB_VIA_T )
{
export_vrml_via( aModel, pcb, (const VIA*) track );
}
else if( track->GetLayer() == B_Cu || track->GetLayer() == F_Cu )
export_vrml_line( aModel, track->GetLayer(),
track->GetStart().x * aModel.scale,
track->GetStart().y * aModel.scale,
track->GetEnd().x * aModel.scale,
track->GetEnd().y * aModel.scale,
track->GetWidth() * aModel.scale );
}
}
示例11: BuildTracksCandidatesList
void CONNECTIONS::BuildTracksCandidatesList( TRACK* aBegin, TRACK* aEnd)
{
m_candidates.clear();
m_firstTrack = m_lastTrack = aBegin;
unsigned ii = 0;
// Count candidates ( i.e. end points )
for( const TRACK* track = aBegin; track; track = track->Next() )
{
if( track->Type() == PCB_VIA_T )
ii++;
else
ii += 2;
m_lastTrack = track;
if( track == aEnd )
break;
}
// Build candidate list
m_candidates.reserve( ii );
for( TRACK* track = aBegin; track; track = track->Next() )
{
CONNECTED_POINT candidate( track, track->GetStart() );
m_candidates.push_back( candidate );
if( track->Type() != PCB_VIA_T )
{
CONNECTED_POINT candidate2( track, track->GetEnd());
m_candidates.push_back( candidate2 );
}
if( track == aEnd )
break;
}
// Sort list by increasing X coordinate,
// and for increasing Y coordinate when items have the same X coordinate
// So candidates to the same location are consecutive in list.
sort( m_candidates.begin(), m_candidates.end(), sortConnectedPointByXthenYCoordinates );
}
示例12: SyncWorld
void PNS_ROUTER::SyncWorld()
{
if( !m_board )
{
TRACEn( 0, "No board attached, aborting sync." );
return;
}
ClearWorld();
m_world = new PNS_NODE();
for( MODULE* module = m_board->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
{
PNS_ITEM* solid = syncPad( pad );
if( solid )
m_world->Add( solid );
}
}
for( TRACK* t = m_board->m_Track; t; t = t->Next() )
{
KICAD_T type = t->Type();
PNS_ITEM* item = NULL;
if( type == PCB_TRACE_T )
item = syncTrack( t );
else if( type == PCB_VIA_T )
item = syncVia( static_cast<VIA*>( t ) );
if( item )
m_world->Add( item );
}
int worstClearance = m_board->GetDesignSettings().GetBiggestClearanceValue();
m_clearanceFunc = new PNS_PCBNEW_CLEARANCE_FUNC( this );
m_world->SetClearanceFunctor( m_clearanceFunc );
m_world->SetMaxClearance( 4 * worstClearance );
}
示例13: build_via_testpoints
/* Extract the D356 record from the vias */
static void build_via_testpoints( BOARD *aPcb,
std::vector <D356_RECORD>& aRecords )
{
wxPoint origin = aPcb->GetAuxOrigin();
// Enumerate all the track segments and keep the vias
for( TRACK *track = aPcb->m_Track; track; track = track->Next() )
{
if( track->Type() == PCB_VIA_T )
{
VIA *via = (VIA*) track;
NETINFO_ITEM *net = track->GetNet();
D356_RECORD rk;
rk.smd = false;
rk.hole = true;
if( net )
rk.netname = net->GetNetname();
else
rk.netname = wxEmptyString;
rk.refdes = wxT("VIA");
rk.pin = wxT("");
rk.midpoint = true; // Vias are always midpoints
rk.drill = via->GetDrillValue();
rk.mechanical = false;
LAYER_ID top_layer, bottom_layer;
via->LayerPair( &top_layer, &bottom_layer );
rk.access = via_access_code( aPcb, top_layer, bottom_layer );
rk.x_location = via->GetPosition().x - origin.x;
rk.y_location = origin.y - via->GetPosition().y;
rk.x_size = via->GetWidth();
rk.y_size = 0; // Round so height = 0
rk.rotation = 0;
rk.soldermask = 3; // XXX always tented?
aRecords.push_back( rk );
}
}
}
示例14: ViaDisplayMode
int PCBNEW_CONTROL::ViaDisplayMode( const TOOL_EVENT& aEvent )
{
KIGFX::PCB_PAINTER* painter =
static_cast<KIGFX::PCB_PAINTER*>( m_frame->GetGalCanvas()->GetView()->GetPainter() );
KIGFX::PCB_RENDER_SETTINGS* settings =
static_cast<KIGFX::PCB_RENDER_SETTINGS*>( painter->GetSettings() );
DISPLAY_OPTIONS* displ_opts = (DISPLAY_OPTIONS*)m_frame->GetDisplayOptions();
// Apply new display options to the GAL canvas
displ_opts->m_DisplayViaFill = !displ_opts->m_DisplayViaFill;
settings->LoadDisplayOptions( displ_opts );
for( TRACK* track = getModel<BOARD>()->m_Track; track; track = track->Next() )
{
if( track->Type() == PCB_VIA_T )
track->ViewUpdate( KIGFX::VIEW_ITEM::GEOMETRY );
}
m_frame->GetGalCanvas()->Refresh();
return 0;
}
示例15: GetBoard
void EDA_3D_CANVAS::buildBoard3DView( GLuint aBoardList, GLuint aBodyOnlyList,
REPORTER* aErrorMessages, REPORTER* aActivity )
{
BOARD* pcb = GetBoard();
// If FL_RENDER_SHOW_HOLES_IN_ZONES is true, holes are correctly removed from copper zones areas.
// If FL_RENDER_SHOW_HOLES_IN_ZONES is false, holes are not removed from copper zones areas,
// but the calculation time is twice shorter.
bool remove_Holes = isEnabled( FL_RENDER_SHOW_HOLES_IN_ZONES );
bool realistic_mode = isRealisticMode();
bool useTextures = isRealisticMode() && isEnabled( FL_RENDER_TEXTURES );
// Number of segments to convert a circle to polygon
// We use 2 values: the first gives a good shape (for instanes rond pads)
// the second is used to speed up calculations, when a poor approximation is acceptable (holes)
const int segcountforcircle = 18;
double correctionFactor = 1.0 / cos( M_PI / (segcountforcircle * 2.0) );
const int segcountLowQuality = 12; // segments to draw a circle with low quality
// to reduce time calculations
// for holes and items which do not need
// a fine representation
double correctionFactorLQ = 1.0 / cos( M_PI / (segcountLowQuality * 2.0) );
SHAPE_POLY_SET bufferPolys; // copper areas: tracks, pads and filled zones areas
// when holes are removed from zones
SHAPE_POLY_SET bufferPcbOutlines; // stores the board main outlines
SHAPE_POLY_SET bufferZonesPolys; // copper filled zones areas
// when holes are not removed from zones
SHAPE_POLY_SET currLayerHoles; // Contains holes for the current layer
SHAPE_POLY_SET allLayerHoles; // Contains holes for all layers
// Build a polygon from edge cut items
wxString msg;
if( !pcb->GetBoardPolygonOutlines( bufferPcbOutlines, allLayerHoles, &msg ) )
{
if( aErrorMessages )
{
msg << wxT("\n") << _("Unable to calculate the board outlines.\n"
"Therefore use the board boundary box.") << wxT("\n\n");
aErrorMessages->Report( msg, REPORTER::RPT_WARNING );
}
}
// Build board holes, with optimization of large holes shape.
buildBoardThroughHolesPolygonList( allLayerHoles, segcountLowQuality, true );
LSET cu_set = LSET::AllCuMask( GetPrm3DVisu().m_CopperLayersCount );
glNewList( aBoardList, GL_COMPILE );
for( LSEQ cu = cu_set.CuStack(); cu; ++cu )
{
LAYER_ID layer = *cu;
// Skip non enabled layers in normal mode,
// and internal layers in realistic mode
if( !is3DLayerEnabled( layer ) )
continue;
if( aActivity )
aActivity->Report( wxString::Format( _( "Build layer %s" ), LSET::Name( layer ) ) );
bufferPolys.RemoveAllContours();
bufferZonesPolys.RemoveAllContours();
currLayerHoles.RemoveAllContours();
// Draw track shapes:
for( TRACK* track = pcb->m_Track; track; track = track->Next() )
{
if( !track->IsOnLayer( layer ) )
continue;
track->TransformShapeWithClearanceToPolygon( bufferPolys,
0, segcountforcircle,
correctionFactor );
// Add blind/buried via holes
if( track->Type() == PCB_VIA_T )
{
VIA *via = static_cast<VIA*>( track );
if( via->GetViaType() == VIA_THROUGH )
continue; // already done
int holediameter = via->GetDrillValue();
int thickness = GetPrm3DVisu().GetCopperThicknessBIU();
int hole_outer_radius = (holediameter + thickness) / 2;
TransformCircleToPolygon( currLayerHoles,
via->GetStart(), hole_outer_radius,
segcountLowQuality );
}
}
// draw pad shapes
for( MODULE* module = pcb->m_Modules; module; module = module->Next() )
{
//.........这里部分代码省略.........