本文整理汇总了C++中TRACK::GetLayerMask方法的典型用法代码示例。如果您正苦于以下问题：C++ TRACK::GetLayerMask方法的具体用法？C++ TRACK::GetLayerMask怎么用？C++ TRACK::GetLayerMask使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类TRACK的用法示例。
在下文中一共展示了TRACK::GetLayerMask方法的2个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: GetTrack
TRACK* GetTrack( TRACK* aStartTrace, const TRACK* aEndTrace,
const wxPoint& aPosition, LAYER_MSK aLayerMask )
{
for( TRACK *PtSegm = aStartTrace; PtSegm != NULL; PtSegm = PtSegm->Next() )
{
if( PtSegm->GetState( IS_DELETED | BUSY ) == 0 )
{
if( aPosition == PtSegm->GetStart() )
{
if( aLayerMask & PtSegm->GetLayerMask() )
return PtSegm;
}
if( aPosition == PtSegm->GetEnd() )
{
if( aLayerMask & PtSegm->GetLayerMask() )
return PtSegm;
}
}
if( PtSegm == aEndTrace )
break;
}
return NULL;
}示例2: doTrackDrc
bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
{
TRACK* track;
wxPoint delta; // lenght on X and Y axis of segments
LAYER_MSK layerMask;
int net_code_ref;
wxPoint shape_pos;
NETCLASS* netclass = aRefSeg->GetNetClass();
/* In order to make some calculations more easier or faster,
* pads and tracks coordinates will be made relative to the reference segment origin
*/
wxPoint origin = aRefSeg->GetStart(); // origin will be the origin of other coordinates
m_segmEnd = delta = aRefSeg->GetEnd() - origin;
m_segmAngle = 0;
layerMask = aRefSeg->GetLayerMask();
net_code_ref = aRefSeg->GetNetCode();
// Phase 0 : Test vias
if( aRefSeg->Type() == PCB_VIA_T )
{
// test if the via size is smaller than minimum
if( aRefSeg->GetShape() == VIA_MICROVIA )
{
if( aRefSeg->GetWidth() < netclass->GetuViaMinDiameter() )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TOO_SMALL_MICROVIA, m_currentMarker );
return false;
}
}
else
{
if( aRefSeg->GetWidth() < netclass->GetViaMinDiameter() )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TOO_SMALL_VIA, m_currentMarker );
return false;
}
}
// test if via's hole is bigger than its diameter
// This test is necessary since the via hole size and width can be modified
// and a default via hole can be bigger than some vias sizes
if( aRefSeg->GetDrillValue() > aRefSeg->GetWidth() )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_VIA_HOLE_BIGGER, m_currentMarker );
return false;
}
// For microvias: test if they are blind vias and only between 2 layers
// because they are used for very small drill size and are drill by laser
// and **only one layer** can be drilled
if( aRefSeg->GetShape() == VIA_MICROVIA )
{
LAYER_NUM layer1, layer2;
bool err = true;
( (SEGVIA*) aRefSeg )->LayerPair( &layer1, &layer2 );
if( layer1 > layer2 )
EXCHG( layer1, layer2 );
// test:
if( layer1 == LAYER_N_BACK && layer2 == LAYER_N_2 )
err = false;
if( layer1 == (m_pcb->GetDesignSettings().GetCopperLayerCount() - 2 )
&& layer2 == LAYER_N_FRONT )
err = false;
if( err )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_MICRO_VIA_INCORRECT_LAYER_PAIR, m_currentMarker );
return false;
}
}
}
else // This is a track segment
{
if( aRefSeg->GetWidth() < netclass->GetTrackMinWidth() )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TOO_SMALL_TRACK_WIDTH, m_currentMarker );
return false;
}
}
// for a non horizontal or vertical segment Compute the segment angle
// in tenths of degrees and its length
if( delta.x || delta.y )
{
// Compute the segment angle in 0,1 degrees
m_segmAngle = ArcTangente( delta.y, delta.x );
//.........这里部分代码省略.........