本文整理汇总了C++中APInt::clearBit方法的典型用法代码示例。如果您正苦于以下问题：C++ APInt::clearBit方法的具体用法？C++ APInt::clearBit怎么用？C++ APInt::clearBit使用的例子？那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类APInt的用法示例。
在下文中一共展示了APInt::clearBit方法的1个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: switch
void X86InstrSema::translateTargetOpcode() {
switch(Opcode) {
default:
llvm_unreachable(
("Unknown X86 opcode found in semantics: " + utostr(Opcode)).c_str());
case X86ISD::CMOV: {
Value *Op1 = getNextOperand(), *Op2 = getNextOperand(),
*Op3 = getNextOperand(), *Op4 = getNextOperand();
assert(Op4 == getReg(X86::EFLAGS) &&
"Conditional mov predicate register isn't EFLAGS!");
(void)Op4;
unsigned CC = cast<ConstantInt>(Op3)->getValue().getZExtValue();
Value *Pred = X86DRS.testCondCode(CC);
registerResult(Builder->CreateSelect(Pred, Op2, Op1));
break;
}
case X86ISD::RET_FLAG: {
// FIXME: Handle ret arg.
/* unsigned Op1 = */ Next();
setReg(X86::RIP, translatePop(8));
Builder->CreateBr(ExitBB);
break;
}
case X86ISD::CMP: {
Value *Op1 = getNextOperand(), *Op2 = getNextOperand();
registerResult(X86DRS.getEFLAGSforCMP(Op1, Op2));
break;
}
case X86ISD::BRCOND: {
Value *Op1 = getNextOperand(), *Op2 = getNextOperand(),
*Op3 = getNextOperand();
assert(Op3 == getReg(X86::EFLAGS) &&
"Conditional branch predicate register isn't EFLAGS!");
(void)Op3;
uint64_t Target = cast<ConstantInt>(Op1)->getValue().getZExtValue();
unsigned CC = cast<ConstantInt>(Op2)->getValue().getZExtValue();
setReg(X86::RIP, Op1);
Builder->CreateCondBr(X86DRS.testCondCode(CC),
getOrCreateBasicBlock(Target),
getOrCreateBasicBlock(getBasicBlockEndAddress()));
break;
}
case X86ISD::CALL: {
Value *Op1 = getNextOperand();
translatePush(Builder->getInt64(CurrentInst->Address + CurrentInst->Size));
insertCall(Op1);
break;
}
case X86ISD::SETCC: {
Value *Op1 = getNextOperand(), *Op2 = getNextOperand();
assert(Op2 == getReg(X86::EFLAGS) &&
"SetCC predicate register isn't EFLAGS!");
(void)Op2;
unsigned CC = cast<ConstantInt>(Op1)->getValue().getZExtValue();
Value *Pred = X86DRS.testCondCode(CC);
registerResult(Builder->CreateZExt(Pred, Builder->getInt8Ty()));
break;
}
case X86ISD::SBB: {
(void)NextVT();
Value *Op1 = getNextOperand(), *Op2 = getNextOperand(),
*Op3 = getNextOperand();
assert(Op3 == getReg(X86::EFLAGS) &&
"SBB borrow register isn't EFLAGS!");
(void)Op3;
Value *Borrow =
Builder->CreateZExt(X86DRS.testCondCode(X86::CF), Op1->getType());
Value *Res = Builder->CreateSub(Op1, Op2);
registerResult(Builder->CreateSub(Res, Borrow));
registerResult(getReg(X86::EFLAGS));
break;
}
case X86ISD::BT: {
Value *Base = getNextOperand();
Value *Op2 = getNextOperand();
Value *Offset = Builder->CreateZExtOrBitCast(Op2, Base->getType());
Value *Bit = Builder->CreateTrunc(Builder->CreateShl(Base, Offset),
Builder->getInt1Ty());
Value *OldEFLAGS = getReg(X86::EFLAGS);
Type *EFLAGSTy = OldEFLAGS->getType();
APInt Mask = APInt::getAllOnesValue(EFLAGSTy->getPrimitiveSizeInBits());
Mask.clearBit(X86::CF);
OldEFLAGS = Builder->CreateAnd(OldEFLAGS, ConstantInt::get(*Ctx, Mask));
Bit = Builder->CreateZExt(Bit, EFLAGSTy);
Bit = Builder->CreateLShr(Bit, X86::CF);
registerResult(Builder->CreateOr(OldEFLAGS, Bit));
break;
}
case X86ISD::BSF: {
(void)NextVT();
Value *Src = getNextOperand();
// If the source is zero, it is undefined behavior as per Intel SDM, but
// most implementations I'm aware of just leave the destination unchanged.
assert((CurrentInst->Inst.getOpcode() >= X86::BSF16rm &&
CurrentInst->Inst.getOpcode() <= X86::BSF64rr) &&
"Unexpected instruction with X86ISD::BSR node!");
Value *IsSrcZero = Builder->CreateIsNull(Src);
//.........这里部分代码省略.........