本文整理汇总了Python中utility.Bits.reset方法的典型用法代码示例。如果您正苦于以下问题：Python Bits.reset方法的具体用法？Python Bits.reset怎么用？Python Bits.reset使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类utility.Bits的用法示例。
在下文中一共展示了Bits.reset方法的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: rra
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def rra(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 0)
cpu.A = Bits.setNthBit((cpu.A >> 1), 7, cpu.CFlag)
cpu.CFlag = Bits.set() if cflag == 1 else Bits.reset()
cpu.HFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("RRA")示例2: _checkInterrupts
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def _checkInterrupts(self):
if self.iff1:
self.halted = Bits.reset()
self.iff1 = Bits.reset()
self.iff2 = Bits.reset()
self.ram[--self.SP] = Bits.limitTo8Bits(self.pc)
self.ram[--self.SP] = self.pc >> 8
self.R += 1
if self.im == 0 or self.im == 1:
self.PC = 0x0038示例3: _or_hl
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def _or_hl(cpu, opcode, logger):
cpu.A = cpu.A | cpu.ram[cpu.HL]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR (HL)")示例4: xorA
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def xorA(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("XOR A")示例5: neg
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def neg(cpu, opcode, logger):
old = cpu.A
cpu.A = 0 - cpu.A
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.set() if old == 0x80 else Bits.reset()
cpu.CFlag = Bits.isZero(old)
cpu.HFlag = Bits.halfCarrySub(0x0, old)
cpu.m_cycles, cpu.t_states = 2, 8
logger.info("NEG")示例6: ldar
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def ldar(cpu, opcode, logger):
cpu.A = cpu.R
cpu.SFlag = Bits.isNegative(cpu.R)
cpu.ZFlag = Bits.isZero(cpu.R)
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.set() if cpu.iff2 == 1 else Bits.reset()
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 9
logger.info("LD A, R")示例7: _or
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def _or(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A | cpu.regs[regInd]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("OR {}".format(IndexToReg.translate8Bit(regInd)))示例8: _and_hl
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def _and_hl(cpu, opcode, logger):
val = cpu.ram[cpu.HL]
cpu.A = cpu.A & val
cpu.HFlag = Bits.set()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("AND (HL)")示例9: xor_n
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def xor_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
cpu.A = old ^ n
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("XOR {:02X}".format(n))示例10: or_n
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def or_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
cpu.A = cpu.A | n
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR {:02X}".format(n))示例11: srl_r
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def srl_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.regs[reg_idx]
cpu.regs[reg_idx] = (old_val >> 1)
last_bit = Bits.getNthBit(old_val, 0)
cpu.CFlag = Bits.set() if last_bit == 1 else Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[reg_idx])
cpu.PVFlag = Bits.isEvenParity(cpu.regs[reg_idx])
cpu.SFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 8
logger.info("SRL {}".format(IndexToReg.translate8Bit(reg_idx)))示例12: rrd
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def rrd(cpu, opcode, logger):
low_a = cpu.A & 0x0F
mem_hl = cpu.ram[cpu.HL]
low_hl = mem_hl & 0x0F
high_hl = (mem_hl & 0xF0) >> 4
cpu.A = (cpu.A & 0xF0) | low_hl
mem_hl = (low_a << 4) | high_hl
cpu.ram[cpu.HL] = mem_hl
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.HFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 5, 18
logger.info("RRD")示例13: add_Hl_rr_c
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def add_Hl_rr_c(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd)
old = cpu.HL
cpu.HL = cpu.HL + val + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
cpu.ZFlag = Bits.isZero(cpu.HL)
cpu.HFlag = Bits.halfCarrySub16(old, cpu.HL)
cpu.PVFlag = Bits.overflow(old, cpu.HL, bits=16)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.set() if (Bits.getNthBit(old, 15) == 1 and
Bits.getNthBit(cpu.HL, 15) == 0) else Bits.reset()
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADC HL, {}".format(IndexToReg.translate16Bit(regInd)))示例14: test_adc_A_mem_HL_takes_7_t_states
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def test_adc_A_mem_HL_takes_7_t_states(self):
cpu = CPU(ROM('\x8e\x05\x06\x07\x08'))
cpu.HL = 0x03
cpu.A = 0x5
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(7, cpu.t_states)示例15: test_add_a_b_with_C_flag_reset_correctly_calculates_value
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import reset [as 别名]
def test_add_a_b_with_C_flag_reset_correctly_calculates_value(self):
cpu = CPU(ROM('\x88'))
cpu.A = 0x22
cpu.B = 0x33
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x55, cpu.A)