本文整理汇总了Python中utility.Bits.isEvenParity方法的典型用法代码示例。如果您正苦于以下问题：Python Bits.isEvenParity方法的具体用法？Python Bits.isEvenParity怎么用？Python Bits.isEvenParity使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类utility.Bits的用法示例。
在下文中一共展示了Bits.isEvenParity方法的8个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: xorA
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isEvenParity [as 别名]
def xorA(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("XOR A")示例2: _or_hl
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isEvenParity [as 别名]
def _or_hl(cpu, opcode, logger):
cpu.A = cpu.A | cpu.ram[cpu.HL]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR (HL)")示例3: _or
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isEvenParity [as 别名]
def _or(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A | cpu.regs[regInd]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("OR {}".format(IndexToReg.translate8Bit(regInd)))示例4: _and_hl
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isEvenParity [as 别名]
def _and_hl(cpu, opcode, logger):
val = cpu.ram[cpu.HL]
cpu.A = cpu.A & val
cpu.HFlag = Bits.set()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("AND (HL)")示例5: xor_n
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isEvenParity [as 别名]
def xor_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
cpu.A = old ^ n
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("XOR {:02X}".format(n))示例6: rrd
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isEvenParity [as 别名]
def rrd(cpu, opcode, logger):
low_a = cpu.A & 0x0F
mem_hl = cpu.ram[cpu.HL]
low_hl = mem_hl & 0x0F
high_hl = (mem_hl & 0xF0) >> 4
cpu.A = (cpu.A & 0xF0) | low_hl
mem_hl = (low_a << 4) | high_hl
cpu.ram[cpu.HL] = mem_hl
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.HFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 5, 18
logger.info("RRD")示例7: srl_r
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isEvenParity [as 别名]
def srl_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.regs[reg_idx]
cpu.regs[reg_idx] = (old_val >> 1)
last_bit = Bits.getNthBit(old_val, 0)
cpu.CFlag = Bits.set() if last_bit == 1 else Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[reg_idx])
cpu.PVFlag = Bits.isEvenParity(cpu.regs[reg_idx])
cpu.SFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 8
logger.info("SRL {}".format(IndexToReg.translate8Bit(reg_idx)))示例8: test_bits_isEvenParity_returns_true_when_valus_has_even_number_of_1s
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isEvenParity [as 别名]
def test_bits_isEvenParity_returns_true_when_valus_has_even_number_of_1s(self):
self.assertTrue(Bits.isEvenParity(3))