本文整理汇总了Python中utility.Bits.isZero方法的典型用法代码示例。如果您正苦于以下问题：Python Bits.isZero方法的具体用法？Python Bits.isZero怎么用？Python Bits.isZero使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类utility.Bits的用法示例。
在下文中一共展示了Bits.isZero方法的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: neg
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def neg(cpu, opcode, logger):
old = cpu.A
cpu.A = 0 - cpu.A
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.set() if old == 0x80 else Bits.reset()
cpu.CFlag = Bits.isZero(old)
cpu.HFlag = Bits.halfCarrySub(0x0, old)
cpu.m_cycles, cpu.t_states = 2, 8
logger.info("NEG")示例2: sbc
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def sbc(cpu, opcode, logger):
logger.info("SBC HL")
regInd = (opcode & 0x30) >> 4
value = 0
if regInd == 0:
value = cpu.BC
elif regInd == 1:
value = cpu.DE
elif regInd == 2:
value = cpu.HL
elif regInd == 3:
value = cpu.SP
oldHL = cpu.HL
logger.info("Old value of HL: " + str(oldHL))
cpu.HL = cpu.HL - value - (1 if cpu.CFlag else 0)
logger.info("New value of HL: " + str(cpu.HL))
cpu.flags[SF] = Bits.signFlag(cpu.HL, bits=16)
cpu.flags[ZF] = Bits.isZero(cpu.HL)
cpu.flags[HF] = Bits.halfCarrySub16(oldHL, cpu.HL)
cpu.flags[PVF] = Bits.overflow(Bits.twos_comp(oldHL, bits=16),
Bits.twos_comp(cpu.HL, bits=16))
cpu.flags[NF] = True
cpu.flags[CF] = Bits.borrow(cpu.HL, bits=16)示例3: dec_at_hl
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def dec_at_hl(cpu, opcode, logger):
old_val = cpu.ram[cpu.HL]
new_val = old_val - 1
cpu.ram[cpu.HL] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("DEC (HL)")示例4: _and
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def _and(cpu, opcode, logger):
logger.info("AND A")
regInd = opcode & 7
cpu.A = cpu.A & cpu.regs[regInd]
cpu.flags[HF] = True
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)示例5: adc_r
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def adc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val + cpu.regs[reg_idx] + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADC A, {}".format(IndexToReg.translate8Bit(reg_idx)))示例6: cp
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def cp(cpu, opcode, logger):
regInd = opcode & 7
value = cpu.A - cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(value)
cpu.CFlag = Bits.carryFlag(value)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.SFlag = Bits.signFlag(value)
cpu.PVFlag = Bits.overflow(value, cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("CP {}".format(IndexToReg.translate8Bit(regInd)))示例7: inc8
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def inc8(cpu, opcode, logger):
logger.info("INC r")
index = ( opcode >> 3 ) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = (cpu.regs[index] + 1 ) & 0xFF
cpu.NFlag = False
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.twos_comp(cpu.regs[index]) < 0示例8: _or_hl
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def _or_hl(cpu, opcode, logger):
cpu.A = cpu.A | cpu.ram[cpu.HL]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR (HL)")示例9: dec_at_ix_d
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def dec_at_ix_d(cpu, opcode, logger):
d = cpu.ram[cpu.PC]
old_val = cpu.ram[cpu.IX+d]
new_val = old_val - 1
cpu.ram[cpu.IX+d] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 6, 23
logger.info("DEC (IX+{:02X})".format(d))示例10: cp_hl
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def cp_hl(cpu, opcode, logger):
value = cpu.A - cpu.ram[cpu.HL]
cpu.ZFlag = Bits.isZero(value)
cpu.CFlag = Bits.carryFlag(value)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.SFlag = Bits.signFlag(value)
cpu.PVFlag = Bits.overflow(value, cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("CP (HL)")示例11: xorA
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def xorA(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("XOR A")示例12: ldar
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def ldar(cpu, opcode, logger):
cpu.A = cpu.R
cpu.SFlag = Bits.isNegative(cpu.R)
cpu.ZFlag = Bits.isZero(cpu.R)
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.set() if cpu.iff2 == 1 else Bits.reset()
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 9
logger.info("LD A, R")示例13: xorA
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def xorA(cpu, opcode, logger):
"""XOR A"""
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[HF] = False
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)
logger.info("XOR A")示例14: _or
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def _or(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A | cpu.regs[regInd]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("OR {}".format(IndexToReg.translate8Bit(regInd)))示例15: sub_n
# 需要导入模块: from utility import Bits [as 别名]
# 或者: from utility.Bits import isZero [as 别名]
def sub_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
value = cpu.A - n
cpu.NFlag = Bits.set()
cpu.ZFlag = Bits.isZero(value)
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.PVFlag = Bits.overflow(cpu.A, value)
cpu.CFlag = Bits.carryFlag(value)
cpu.A = value
logger.info("SUB {:02X}".format(n))