本文整理汇总了Python中utility.Bits类的典型用法代码示例。如果您正苦于以下问题：Python Bits类的具体用法？Python Bits怎么用？Python Bits使用的例子？那么恭喜您, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了Bits类的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: rlca
def rlca(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 7)
cpu.A = Bits.setNthBit(cpu.A << 1, 0, cflag)
cpu.CFlag = Bits.set() if cflag != 0 else Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("RLCA")示例2: test_jr_z_does_not_change_the_z_flag
def test_jr_z_does_not_change_the_z_flag(self):
cpu = CPU(ROM('\x28\x00\x28\x00'))
cpu.ZFlag = Bits.reset()
cpu.readOp()
self.assertFalse(cpu.ZFlag)
cpu.ZFlag = Bits.set()
cpu.readOp()
self.assertTrue(cpu.ZFlag)示例3: cpl
def cpl(cpu, opcode, logger):
old = cpu.A
new = ~old
cpu.A = new
cpu.HFlag = Bits.set()
cpu.NFlag = Bits.set()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("CPL")示例4: _checkInterrupts
def _checkInterrupts(self):
if self.iff1:
self.halted = Bits.reset()
self.iff1 = Bits.reset()
self.iff2 = Bits.reset()
self.ram[--self.SP] = Bits.limitTo8Bits(self.pc)
self.ram[--self.SP] = self.pc >> 8
self.R += 1
if self.im == 0 or self.im == 1:
self.PC = 0x0038示例5: dec_at_hl
def dec_at_hl(cpu, opcode, logger):
old_val = cpu.ram[cpu.HL]
new_val = old_val - 1
cpu.ram[cpu.HL] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("DEC (HL)")示例6: _and
def _and(cpu, opcode, logger):
logger.info("AND A")
regInd = opcode & 7
cpu.A = cpu.A & cpu.regs[regInd]
cpu.flags[HF] = True
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)示例7: add_iy_rr
def add_iy_rr(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd, iy=True)
old = cpu.IY
cpu.IY = cpu.IY + val
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.carryFlagAdd16(old, cpu.IY)
cpu.CFlag = Bits.overflow(old, cpu.IY, bits=16)
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADD IY, {}".format(IndexToReg.translate16Bit(regInd)))示例8: inc8
def inc8(cpu, opcode, logger):
logger.info("INC r")
index = ( opcode >> 3 ) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = (cpu.regs[index] + 1 ) & 0xFF
cpu.NFlag = False
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.twos_comp(cpu.regs[index]) < 0示例9: dec_at_ix_d
def dec_at_ix_d(cpu, opcode, logger):
d = cpu.ram[cpu.PC]
old_val = cpu.ram[cpu.IX+d]
new_val = old_val - 1
cpu.ram[cpu.IX+d] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 6, 23
logger.info("DEC (IX+{:02X})".format(d))示例10: adc_r
def adc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val + cpu.regs[reg_idx] + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADC A, {}".format(IndexToReg.translate8Bit(reg_idx)))示例11: cp
def cp(cpu, opcode, logger):
regInd = opcode & 7
logger.info(regInd)
value = cpu.A - cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(value)
cpu.flags[CF] = Bits.carryFlag(value)
cpu.flags[NF] = True
cpu.flags[HF] = Bits.halfCarrySub(cpu.A, value)
cpu.flags[SF] = Bits.signFlag(value)
cpu.flags[PVF] = Bits.overflow(cpu.A, value)
logger.info("CP r")示例12: xorA
def xorA(cpu, opcode, logger):
"""XOR A"""
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[HF] = False
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)
logger.info("XOR A")示例13: sub_n
def sub_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
value = cpu.A - n
cpu.NFlag = Bits.set()
cpu.ZFlag = Bits.isZero(value)
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.PVFlag = Bits.overflow(cpu.A, value)
cpu.CFlag = Bits.carryFlag(value)
cpu.A = value
logger.info("SUB {:02X}".format(n))示例14: add16
def add16(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
value = cpu.Reg16(regInd)
oldHL = cpu.HL
cpu.HL = cpu.HL + value
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag16(oldHL, cpu.HL)
cpu.HFlag = Bits.carryFlag16(oldHL, cpu.HL, bits=11)
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("ADD HL, {}".format(IndexToReg.translate16Bit(regInd)))示例15: inc8
def inc8(cpu, opcode, logger):
index = (opcode >> 3) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = Bits.limitTo8Bits(cpu.regs[index] + 1)
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.isNegative(cpu.regs[index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("INC {}".format(IndexToReg.translate8Bit(index)))