Python Project.synthesise方法代码示例

# 需要导入模块: from chiptools.core.project import Project [as 别名]
# 或者: from chiptools.core.project.Project import synthesise [as 别名]
# to 'False', this tells the synthesis tool not to try to synthesise this file.
# If not specified, 'synthesise' will default to 'True'
project.add_file(
    'tb_axi_lite_slave_example.v',
    library='lib_tb_example',
    synthesise=False
)

if __name__ == '__main__':

    interactive = True  # Set True to load the ChipTools CLI

    if interactive:
        # ChipTools provides a command line interface to allow you to perform
        # actions on the project such as synthesis and simulation interactively.
        # It can be launched by importing the CommandLine from chiptools.core.cli
        # and executing the cmdloop() method - the project is passed to the
        # CommandLine constructor. Launch the ChipTools command line with the
        # project we just configured:
        from chiptools.core.cli import CommandLine
        CommandLine(project).cmdloop()
    else:
        # Run the automated unit tests on the project:
        project.run_tests(tool_name='vivado')
        # Synthesise the project:
        project.synthesise(
            library='lib_example',
            entity='axi_lite_slave_example',
            tool_name='vivado'
        )

# 需要导入模块: from chiptools.core.project import Project [as 别名]
# 或者: from chiptools.core.project.Project import synthesise [as 别名]

#.........这里部分代码省略.........
                    'Loading {0} in current working directory: {1}'.format(
                        path,
                        os.getcwd()
                    )
                )
                XmlProjectParser.load_project(path, self.project)
            except:
                log.error('The project could not be loaded due to an error:')
                log.error(traceback.format_exc())
        else:
            log.error('File not found: {0}'.format(path))

    @wraps_do_commands
    def do_exit(self, command):
        return True

    @wraps_do_commands
    def do_compile(self, command):
        self.project.compile()

    @wraps_do_commands
    def do_show_synthesis_fileset(self, command):
        """Print out the synthesis file set"""
        items = self.project.get_synthesis_fileset().items()
        if len(items) == 0:
            log.info('There are no synthesisable files loaded.')
            return
        for libName, fileList in items:
            log.info('Library: ' + libName)
            for file in fileList:
                log.info('\t\t' + file.path)

    @wraps_do_commands
    def do_synthesise(self, command):
        """Synthesise the design using the chosen synthesis tool and report any
        errors Example: (Cmd) simulate my_library.my_entity"""
        command_elems = command.split(' ')
        fpga_part = None
        if len(command_elems) == 3:
            target, tool_name, fpga_part = command_elems
        elif len(command_elems) == 2:
            target, tool_name = command_elems
        else:
            target = command_elems[0]
            tool_name = None

        try:
            library, entity = target.split('.')
        except ValueError:
            log.error('Command \"' + command + '\" not understood.')
            log.error(
                "Please specify a library and entity.\n" +
                "Example: (Cmd) synthesise my_library.my_entity [tool_name]"
            )
            return

        self.project.synthesise(
            library,
            entity,
            tool_name=tool_name,
            fpga_part=fpga_part
        )

    @wraps_do_commands
    def do_run_preprocessors(self, command):
        """For each project file in the design run any associated

# 需要导入模块: from chiptools.core.project import Project [as 别名]
# 或者: from chiptools.core.project.Project import synthesise [as 别名]
)

interactive = False

if interactive:
    # ChipTools provides a command line interface to allow you to perform
    # actions on the project such as synthesis and simulation interactively.
    # It can be launched by importing the CommandLine from chiptools.core.cli
    # and executing the cmdloop() method - the project is passed to the
    # CommandLine constructor. Launch the ChipTools command line with the
    # project we just configured:
    from chiptools.core.cli import CommandLine
    CommandLine(project).cmdloop()
else:
    # actions can be performed on the project directly using the simulate,
    # synthesise or run_tests methods:
    # Simulate the project interactively by presenting the simulator GUI:
    #project.simulate(
    #    library='lib_tb_max_hold',
    #    entity='tb_max_hold',
    #    gui=True,
    #    tool_name='modelsim'
    #)
    ## Run the automated unit tests on the project:
    #project.run_tests(tool_name='isim')
    ## Synthesise the project:
    project.synthesise(
        library='lib_max_hold',
        entity='max_hold',
        tool_name='vivado'
    )