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Python Project.simulate方法代码示例

本文整理汇总了Python中chiptools.core.project.Project.simulate方法的典型用法代码示例。如果您正苦于以下问题:Python Project.simulate方法的具体用法?Python Project.simulate怎么用?Python Project.simulate使用的例子?那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在chiptools.core.project.Project的用法示例。


在下文中一共展示了Project.simulate方法的1个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的Python代码示例。

示例1: CommandLine

# 需要导入模块: from chiptools.core.project import Project [as 别名]
# 或者: from chiptools.core.project.Project import simulate [as 别名]

#.........这里部分代码省略.........
                        os.getcwd()
                    )
                )
                XmlProjectParser.load_project(path, self.project)
            except:
                log.error('The project could not be loaded due to an error:')
                log.error(traceback.format_exc())
        else:
            log.error('File not found: {0}'.format(path))

    @wraps_do_commands
    def do_exit(self, command):
        return True

    @wraps_do_commands
    def do_compile(self, command):
        self.project.compile()

    @wraps_do_commands
    def do_show_synthesis_fileset(self, command):
        """Print out the synthesis file set"""
        items = self.project.get_synthesis_fileset().items()
        if len(items) == 0:
            log.info('There are no synthesisable files loaded.')
            return
        for libName, fileList in items:
            log.info('Library: ' + libName)
            for file in fileList:
                log.info('\t\t' + file.path)

    @wraps_do_commands
    def do_synthesise(self, command):
        """Synthesise the design using the chosen synthesis tool and report any
        errors Example: (Cmd) simulate my_library.my_entity"""
        command_elems = command.split(' ')
        fpga_part = None
        if len(command_elems) == 3:
            target, tool_name, fpga_part = command_elems
        elif len(command_elems) == 2:
            target, tool_name = command_elems
        else:
            target = command_elems[0]
            tool_name = None

        try:
            library, entity = target.split('.')
        except ValueError:
            log.error('Command \"' + command + '\" not understood.')
            log.error(
                "Please specify a library and entity.\n" +
                "Example: (Cmd) synthesise my_library.my_entity [tool_name]"
            )
            return

        self.project.synthesise(
            library,
            entity,
            tool_name=tool_name,
            fpga_part=fpga_part
        )

    @wraps_do_commands
    def do_run_preprocessors(self, command):
        """For each project file in the design run any associated
        preprocessors. You can use this command to test that a preprocessor is
        running on your file correctly. Preprocessors are called automatically
开发者ID:hoangt,项目名称:chiptools,代码行数:70,代码来源:cli.py


注:本文中的chiptools.core.project.Project.simulate方法示例由纯净天空整理自Github/MSDocs等开源代码及文档管理平台,相关代码片段筛选自各路编程大神贡献的开源项目,源码版权归原作者所有,传播和使用请参考对应项目的License;未经允许,请勿转载。