本文整理汇总了Python中chiptools.core.project.Project.add_generic方法的典型用法代码示例。如果您正苦于以下问题：Python Project.add_generic方法的具体用法？Python Project.add_generic怎么用？Python Project.add_generic使用的例子？那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类chiptools.core.project.Project的用法示例。
在下文中一共展示了Project.add_generic方法的1个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: for
# 需要导入模块: from chiptools.core.project import Project [as 别名]
# 或者: from chiptools.core.project.Project import add_generic [as 别名]
project.add_config_dict(**config)
# Some unit tests have been written for the component and stored in
# basic_unit_test.py. The Project class provides an 'add_unittest' method for
# adding unit tests to the project, it expects a path to the unit test file.
project.add_unittest('basic_unit_test.py')
# The constraints are added to the project using the add_constraints method.
# The optional 'flow' argument is used to explicitly identify which synthesis
# flow the constraints are intended for (the default is to infer supported
# flows from the file extension).
# project.add_constraints('axi_lite_slave_example.xdc', flow='vivado')
# Synthesis generics can be assigned via the add_generic command, in this
# example we set the data_Width generic to 32:
project.add_generic('data_width', 32)
# Source files for the component are added to the project. The Project
# 'add_file' method accepts a file path and library name, if no library is
# specified it will default to 'work'. Other file attributes are available but
# not covered in this example.
project.add_file('axi_lite_slave_example.v', library='lib_example')
# When adding the testbench file we supply a 'synthesise' attribute and set it
# to 'False', this tells the synthesis tool not to try to synthesise this file.
# If not specified, 'synthesise' will default to 'True'
project.add_file(
'tb_axi_lite_slave_example.v',
library='lib_tb_example',
synthesise=False
)