本文整理汇总了Python中chiptools.core.project.Project.get_fpga_part方法的典型用法代码示例。如果您正苦于以下问题：Python Project.get_fpga_part方法的具体用法？Python Project.get_fpga_part怎么用？Python Project.get_fpga_part使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类chiptools.core.project.Project的用法示例。
在下文中一共展示了Project.get_fpga_part方法的3个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: test_project_part
# 需要导入模块: from chiptools.core.project import Project [as 别名]
# 或者: from chiptools.core.project.Project import get_fpga_part [as 别名]
def test_project_part(self):
project = Project()
project.load_project(self.project_path)
# Check project part
self.assertEqual(
self.project_part,
project.get_fpga_part()
)示例2: testProjectPart
# 需要导入模块: from chiptools.core.project import Project [as 别名]
# 或者: from chiptools.core.project.Project import get_fpga_part [as 别名]
def testProjectPart(self):
project = Project()
XmlProjectParser.load_project(self.project_path, project)
# Check project part
self.assertEqual(
self.project_part,
project.get_fpga_part()
)示例3: CommandLine
# 需要导入模块: from chiptools.core.project import Project [as 别名]
# 或者: from chiptools.core.project.Project import get_fpga_part [as 别名]
#.........这里部分代码省略.........
(SEP * 2 + '{:<15}: ' + term.green('{:<35}') + '\n').format(
k,
v
) for k, v in (
self.project.get_simulator_library_dependencies().items()
)
) +
'\n' +
term.yellow(term.bold('Project Configuration: ')) +
term.green('%(project)s') + '\n' +
term.darkgray(SEP + 'Simulation directory set to:\n') +
SEP * 2 + term.green('%(simulation_directory)s') + '\n' +
term.darkgray(SEP + 'Using the simulation tool:\n') +
SEP * 2 + term.green('%(simulation_tool_name)s') + '\n' +
term.darkgray(SEP + 'Synthesis directory set to:\n') +
SEP * 2 + term.green('%(synthesis_directory)s') + '\n' +
term.darkgray(SEP + 'Using the synthesis tool:\n') +
SEP * 2 + term.green('%(synthesis_tool_name)s') + '\n' +
term.darkgray(SEP + 'Targeting FPGA part:\n') +
SEP * 2 + term.green('%(fpga_part)s') + '\n' +
term.darkgray(SEP + 'Using synthesis generic binding:\n') +
SEP * 2 + term.green('%(synthesis_generics)s') + '\n' +
term.darkgray(SEP + 'Modelsim Specific Arguments:\n') +
SEP * 2 + 'vsim: ' + term.green('%(modelsim_vsim_args)s') + '\n'
)
print(msg % dict(
working_directory=os.getcwd(),
options=self.project.get_system_config_path(),
simulation_directory=self.project.get_simulation_directory(),
simulation_tool_name=self.project.get_simulation_tool_name(),
synthesis_directory=self.project.get_synthesis_directory(),
synthesis_tool_name=self.project.get_synthesis_tool_name(),
fpga_part=self.project.get_fpga_part(),
modelsim_vsim_args=self.project.get_tool_arguments(
'modelsim',
'simulate'
),
project='',
synthesis_generics=''.join(
str(k) + ':' + str(v) + ', ' for k, v in
self.project.get_generics().items()
))
)
@wraps_do_commands
def do_show_tests(self, command):
"""
Show the tests available in the current project.
"""
tests = self.project.get_tests()
if len(tests) == 0:
log.info('There are no tests available.')
return
testUniqueId = 0
for file_object in tests:
file_name = os.path.basename(file_object.path)
print(term.yellow(file_name))
for test_group in file_object.testsuite:
for testId, test in enumerate(test_group):
if testId == 0:
print(
SEP + term.green(str(test.__class__.__name__))
)