Python Tree.insert_root方法代码示例

# 需要导入模块: import Tree [as 别名]
# 或者: from Tree import insert_root [as 别名]
def main():
	# Array with all SO signal names, generated from Interlock Strings sheet.
	soArray = generate_soArray()
	# Array with all DO/DI signal names, generated from the Interlock Matrix sheet.
	doiArray = matrixSheet.row_values(2, 14, 146)

	# Array containing entire column 'A' from Interlock Strings sheet.
	# The array is used to determine row numbers corresponding to 'ILK',
	# 'Where Used', and 'I/O memebers' data.
	filterArray = stringsSheet.col_values(0)

	# Might need update <--
	for index, item in enumerate(filterArray):
		if item == "Interlock Number:":
			interlockNumArray.append(index)
		elif item == "Where Used:":
			whereUsedNumArray.append(index)
		elif item == "I/O Members:":
			ioMemNumArray.append(index)

	# Dictionary mapping signals to their equations
	dependencyMap = dict()

	for soName in soArray:
		dependencyMap[soName] = []
		
		# Looks for soName occurence in the Interlock Strings sheet.
		# After the occurence is detemined, the position is used to match
		# the signal with its main ILK.
		for index, item in enumerate(whereUsedNumArray):
			if index == (len(whereUsedNumArray) - 1):
				searchCol1 = stringsSheet.col_values(11, item+1)
				searchCol2 = stringsSheet.col_values(26, item+1)
			else:
				searchCol1 = stringsSheet.col_values(11, item+1, interlockNumArray[index+1])
				searchCol2 = stringsSheet.col_values(26, item+1, interlockNumArray[index+1])

			found = match(searchCol1, searchCol2, soName)
			if not found:
				continue
			break
		
		# TODO: can raise exception if soName not found in the sheet.
		
		# Appends the main ILK at the front of the array.
		dependencyMap[soName].append(stringsSheet.cell(interlockNumArray[index], 11).value)
		# Beginning row number for I/O members of the given ILK.
		start = ioMemNumArray[index] + 1
		# End row number for I/O members of the given ILK.
		stop = whereUsedNumArray[index] - 1
		# Column 'L' of the I/O members.
		c1 = stringsSheet.col_values(11, start, stop)
		# Column 'AA' of the I/O members.
		c2 = stringsSheet.col_values(26, start, stop)
		# Appends DO/DI signals from the first column.
		for doName in c1:
			if doName == '':
				continue
			dependencyMap[soName].append(doName)
		# Appends DO/DI signals from the second column.
		for doName in c2:
			if doName == '':
				continue
			dependencyMap[soName].append(doName)

	# For each SO signal, we flatten the equation, starting from the top,
	# i.e., the main ILK name, and its corresponding I/O members.	
	for soName in soArray:
		array = dependencyMap[soName]
		# main ILK
		ilk = array[0]
		mainIlk = ilk
		# Array of DO/DI signals.
		array = array[1:]

		# Separate check for ILK_01, since it only contains one I/O member.
		# Might need update <--
		if mainIlk == 'ILK_01':
			dependencyMap[soName] = [mainIlk, 'DI_000']
			continue

		tree = Tree()
		# Main ILK inserted at root, and p is the pointer to the root.
		p = tree.insert_root(ilk)
		
		# Checks if any ILKs are present in the tree which we haven't
		# accounted for (not "visited" even once), and flattens the
		# equation by finding that ILK's I/O members, and so on...
		while tree.has_ilk():
			pointer, ilk = tree.get_ilk()
			loop(tree, pointer, ilk)

		# Ensures proper traversal order.
		# New ILK branches are always on the left, and the continuing I/O
		# members are on the right.
		tree.reverse_children()

		# New array with all signals for a given soName, with these
		# signals formatted properly (i.e., NOT changed to ~, ILKs skipped,
		# and parenthesis in place for logic reduction).
#.........这里部分代码省略.........