本文整理汇总了Python中vunit.project.Project.get_library方法的典型用法代码示例。如果您正苦于以下问题：Python Project.get_library方法的具体用法？Python Project.get_library怎么用？Python Project.get_library使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类vunit.project.Project的用法示例。
在下文中一共展示了Project.get_library方法的2个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: TestProject
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import get_library [as 别名]
#.........这里部分代码省略.........
self.assert_has_component_instantiation("top.vhd", "foo2")
self.assert_compiles("comp1.vhd", before="top.vhd")
self.assert_compiles("comp2.vhd", before="top.vhd")
def test_get_dependencies_in_compile_order_without_target(self):
self.create_dummy_three_file_project(False)
deps = self.project.get_dependencies_in_compile_order(target=None)
self.assertEqual(len(deps), 3)
self.assertTrue(deps[0] == self.project.get_source_files_in_order()[0])
self.assertTrue(deps[1] == self.project.get_source_files_in_order()[1])
self.assertTrue(deps[2] == self.project.get_source_files_in_order()[2])
def test_get_dependencies_in_compile_order_with_target(self):
self.create_dummy_three_file_project(False)
deps = self.project.get_dependencies_in_compile_order(target=self.project.get_source_files_in_order()[1].name)
self.assertEqual(len(deps), 2)
self.assertTrue(deps[0] == self.project.get_source_files_in_order()[0])
self.assertTrue(deps[1] == self.project.get_source_files_in_order()[1])
# To test that indirect dependencies are included
deps = self.project.get_dependencies_in_compile_order(target=self.project.get_source_files_in_order()[2].name)
self.assertEqual(len(deps), 3)
self.assertTrue(deps[0] == self.project.get_source_files_in_order()[0])
self.assertTrue(deps[1] == self.project.get_source_files_in_order()[1])
self.assertTrue(deps[2] == self.project.get_source_files_in_order()[2])
def test_has_verilog_module(self):
self.project.add_library("lib", "lib_path")
self.add_source_file("lib", "module.v", """\
module name;
endmodule
""")
library = self.project.get_library("lib")
modules = library.get_modules()
self.assertEqual(len(modules), 1)
def test_finds_verilog_package_dependencies(self):
self.project.add_library("lib", "lib_path")
self.add_source_file("lib", "pkg.sv", """\
package pkg;
endpackage
""")
self.add_source_file("lib", "module.sv", """\
module name;
import pkg::*;
endmodule
""")
self.assert_compiles("pkg.sv", before="module.sv")
def test_finds_verilog_module_instantiation_dependencies(self):
self.project.add_library("lib", "lib_path")
self.add_source_file("lib", "module1.sv", """\
module module1;
endmodule
""")
self.add_source_file("lib", "module2.sv", """\
module module2;
module1 inst();
endmodule
""")
self.assert_compiles("module1.sv", before="module2.sv")
def test_finds_verilog_include_dependencies(self):
def create_project():
"""示例2: TestProject
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import get_library [as 别名]
#.........这里部分代码省略.........
""")
for lib in ["lib1", "lib2"]:
self.project.add_library(lib, lib + "_path")
pkgs.append(self.add_source_file(lib, "pkg.vhd", """
library lib;
use lib.other_pkg.all;
package pkg is
end package pkg;
"""))
second_pkgs.append(self.add_source_file(lib, lib + "_pkg.vhd", """
use work.pkg.all;
package second_pkg is
end package second_pkg;
"""))
self.assertNotEqual(self.hash_file_name_of(pkgs[0]),
self.hash_file_name_of(pkgs[1]))
self.assertEqual(len(self.project.get_files_in_compile_order()), 5)
self.assert_compiles(other_pkg, before=pkgs[0])
self.assert_compiles(other_pkg, before=pkgs[1])
self.assert_compiles(pkgs[0], before=second_pkgs[0])
self.assert_compiles(pkgs[1], before=second_pkgs[1])
def test_has_verilog_module(self):
self.project.add_library("lib", "lib_path")
self.add_source_file("lib", "module.v", """\
module name;
endmodule
""")
library = self.project.get_library("lib")
modules = library.get_modules()
self.assertEqual(len(modules), 1)
def test_finds_verilog_package_import_dependencies(self):
self.project.add_library("lib", "lib_path")
pkg = self.add_source_file("lib", "pkg.sv", """\
package pkg;
endpackage
""")
module = self.add_source_file("lib", "module.sv", """\
module name;
import pkg::*;
endmodule
""")
self.assert_compiles(pkg, before=module)
def test_finds_verilog_package_reference_dependencies(self):
self.project.add_library("lib", "lib_path")
pkg = self.add_source_file("lib", "pkg.sv", """\
package pkg;
endpackage
""")
module = self.add_source_file("lib", "module.sv", """\
module name;
pkg::func();
endmodule
""")
self.assert_compiles(pkg, before=module)
def test_finds_verilog_module_instantiation_dependencies(self):
self.project.add_library("lib", "lib_path")
module1 = self.add_source_file("lib", "module1.sv", """\