本文整理汇总了Python中vunit.project.Project.add_library方法的典型用法代码示例。如果您正苦于以下问题：Python Project.add_library方法的具体用法？Python Project.add_library怎么用？Python Project.add_library使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类vunit.project.Project的用法示例。
在下文中一共展示了Project.add_library方法的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: test_compile_project_vhdl_2002
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-v200x -extv200x',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet',
'-nclibdirname ""',
'-makelib lib_path',
'"file.vhd"',
'-endlib'])示例2: test_compile_project_verilog_define
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_verilog_define(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'-work',
'lib',
'file.v',
'-L', 'lib',
'+define+defname=defval'],
simif._compile_output_consumer) # pylint: disable=protected-access示例3: test_compile_project_verilog_hdlvar
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn UEXPSC',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet',
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-define defname=defval',
'-nclibdirname ""',
'-makelib lib',
'"file.v"',
'-endlib'])示例4: test_add_source_file_detects_illegal_vhdl_standard
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_add_source_file_detects_illegal_vhdl_standard(self):
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
self.assertRaises(ValueError, project.add_source_file, "file.vhd",
library_name="lib", file_type='vhdl', vhdl_standard='2007')示例5: test_compile_project_verilog_coverage
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_verilog_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-work',
'lib',
'file.v',
'-L', 'lib'])示例6: test_compile_project_vhdl_2002
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname ""',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)示例7: test_compile_project_verilog_hdlvar
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_verilog_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
"-define defname=defval",
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)示例8: test_compile_project_vhdl_coverage
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_vhdl_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-2008',
'-work',
'lib',
'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access示例9: test_compile_project_vhdl_extra_flags
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_vhdl_extra_flags(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'])示例10: test_compile_project_verilog_error
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_verilog_error(self):
simif = GHDLInterface(prefix="prefix")
write_file("file.v", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.v", "lib", file_type="verilog")
self.assertRaises(CompileError, simif.compile_project, project, vhdl_standard="2008")示例11: test_order_of_adding_libraries_is_kept
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_order_of_adding_libraries_is_kept(self):
for order in itertools.combinations(range(4), 4):
project = Project()
for idx in order:
project.add_library("lib%i" % idx, "lib%i_path" % idx)
library_names = [lib.name for lib in project.get_libraries()]
self.assertEqual(library_names, ["lib%i" % idx for idx in order])示例12: test_add_source_file_has_vhdl_standard
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_add_source_file_has_vhdl_standard(self):
write_file("file.vhd", "")
for std in ('93', '2002', '2008'):
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd",
library_name="lib", file_type='vhdl', vhdl_standard=std)
self.assertEqual(source_file.get_vhdl_standard(), std)示例13: test_compile_project_93
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_93(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93")
simif.compile_project(project)
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=93', '-Plib_path', 'file.vhd'])示例14: test_compile_project_extra_flags
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_extra_flags(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("ghdl.flags", ["custom", "flags"])
simif.compile_project(project)
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib', '--std=08',
'-Plib_path', 'custom', 'flags', 'file.vhd'])示例15: test_compile_project_2002
# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_library [as 别名]
def test_compile_project_2002(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2002")
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=02', '-Plib_path', 'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access