Python Project.add_source_file方法代码示例

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_project_verilog_define(self, process, run_command):
        write_file("modelsim.ini", """
[Library]
                   """)
        modelsim_ini = join(self.output_path, "modelsim.ini")
        simif = ModelSimInterface(prefix="prefix",
                                  modelsim_ini=modelsim_ini,
                                  persistent=False)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.v", "")
        project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
        simif.compile_project(project, vhdl_standard="2008")
        process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
        run_command.assert_called_once_with([join('prefix', 'vlog'),
                                             '-sv',
                                             '-quiet',
                                             '-modelsimini',
                                             modelsim_ini,
                                             '-work',
                                             'lib',
                                             'file.v',
                                             '-L', 'lib',
                                             '+define+defname=defval'],
                                            simif._compile_output_consumer)  # pylint: disable=protected-access

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
 def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
     run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
     self.assertEqual(
         read_file(args_file).splitlines(),
         [
             "-compile",
             "-nocopyright",
             "-licqueue",
             "-nowarn DLCPTH",
             "-nowarn DLCVAR",
             "-v200x -extv200x",
             "-work work",
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
             "-quiet",
             '-nclibdirname ""',
             "-makelib lib_path",
             '"file.vhd"',
             "-endlib",
         ],
     )

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_project_vhdl_coverage(self, process, run_command):
        write_file("modelsim.ini", """
[Library]
                   """)
        modelsim_ini = join(self.output_path, "modelsim.ini")
        simif = ModelSimInterface(prefix="prefix",
                                  modelsim_ini=modelsim_ini,
                                  coverage="best",
                                  persistent=False)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.vhd", "")
        project.add_source_file("file.vhd", "lib", file_type="vhdl")
        simif.compile_project(project, vhdl_standard="2008")
        process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
        run_command.assert_called_once_with([join('prefix', 'vcom'),
                                             '-quiet',
                                             '-modelsimini',
                                             modelsim_ini,
                                             '+cover=best',
                                             '-2008',
                                             '-work',
                                             'lib',
                                             'file.vhd'],
                                            simif._compile_output_consumer)  # pylint: disable=protected-access

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
 def test_compile_project_verilog_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
     run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
     self.assertEqual(
         read_file(args_file).splitlines(),
         [
             "-compile",
             "-nocopyright",
             "-licqueue",
             "-nowarn UEXPSC",
             "-nowarn DLCPTH",
             "-nowarn DLCVAR",
             "-work work",
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-hdlvar "custom_hdlvar"',
             '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
             "-quiet",
             '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
             "-define defname=defval",
             '-nclibdirname ""',
             "-makelib lib",
             '"file.v"',
             "-endlib",
         ],
     )

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_project_verilog_coverage(self, process, run_command):
        write_file("modelsim.ini", """
[Library]
                   """)
        modelsim_ini = join(self.output_path, "modelsim.ini")
        simif = ModelSimInterface(prefix="prefix",
                                  modelsim_ini=modelsim_ini,
                                  coverage="best",
                                  persistent=False)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.v", "")
        project.add_source_file("file.v", "lib", file_type="verilog")
        simif.compile_project(project)
        process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
        run_command.assert_called_once_with([join('prefix', 'vlog'),
                                             '-sv',
                                             '-quiet',
                                             '-modelsimini',
                                             modelsim_ini,
                                             '+cover=best',
                                             '-work',
                                             'lib',
                                             'file.v',
                                             '-L', 'lib'])

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
 def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
     check_output.assert_called_once_with(
         [join('prefix', 'irun'), '-f', args_file],
         env=simif.get_env())
     self.assertEqual(read_file(args_file).splitlines(),
                      ['-compile',
                       '-nocopyright',
                       '-licqueue',
                       '-nowarn DLCPTH',
                       '-nowarn DLCVAR',
                       '-v200x -extv200x',
                       '-work work',
                       '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                       '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
                       '-quiet',
                       '-nclibdirname ""',
                       '-makelib lib_path',
                       '"file.vhd"',
                       '-endlib'])

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
 def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
     check_output.assert_called_once_with(
         [join('prefix', 'irun'), '-f', args_file],
         env=simif.get_env())
     self.assertEqual(read_file(args_file).splitlines(),
                      ['-compile',
                       '-nocopyright',
                       '-licqueue',
                       '-nowarn UEXPSC',
                       '-nowarn DLCPTH',
                       '-nowarn DLCVAR',
                       '-work work',
                       '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                       '-hdlvar "custom_hdlvar"',
                       '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
                       '-quiet',
                       '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
                       '-define defname=defval',
                       '-nclibdirname ""',
                       '-makelib lib',
                       '"file.v"',
                       '-endlib'])

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_project_verilog_error(self):
        simif = GHDLInterface(prefix="prefix")
        write_file("file.v", "")

        project = Project()
        project.add_library("lib", "lib_path")
        project.add_source_file("file.v", "lib", file_type="verilog")
        self.assertRaises(CompileError, simif.compile_project, project, vhdl_standard="2008")

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_project_93(self, run_command):  # pylint: disable=no-self-use
        simif = GHDLInterface(prefix="prefix")
        write_file("file.vhd", "")

        project = Project()
        project.add_library("lib", "lib_path")
        project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93")
        simif.compile_project(project)
        run_command.assert_called_once_with(
            [join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
             '--std=93', '-Plib_path', 'file.vhd'])

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_project_2002(self, run_command):  # pylint: disable=no-self-use
        simif = GHDLInterface(prefix="prefix")
        write_file("file.vhd", "")

        project = Project()
        project.add_library("lib", "lib_path")
        project.add_source_file("file.vhd", "lib", file_type="vhdl")
        simif.compile_project(project, vhdl_standard="2002")
        run_command.assert_called_once_with(
            [join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
             '--std=02', '-Plib_path', 'file.vhd'],
            simif._compile_output_consumer)  # pylint: disable=protected-access

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_project_vhdl_extra_flags(self, process, run_command):
        write_file("modelsim.ini", """
[Library]
                   """)
        modelsim_ini = join(self.output_path, "modelsim.ini")
        simif = ModelSimInterface(prefix="prefix",
                                  modelsim_ini=modelsim_ini,
                                  persistent=False)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.vhd", "")
        source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
        source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
        simif.compile_project(project)
        process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
        run_command.assert_called_once_with([join('prefix', 'vcom'),
                                             '-quiet',
                                             '-modelsimini',
                                             modelsim_ini,
                                             'custom',
                                             'flags',
                                             '-2008',
                                             '-work',
                                             'lib',
                                             'file.vhd'])

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_source_files(self):
        simif = create_simulator_interface()
        simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]])
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file1.vhd", "")
        file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
        write_file("file2.vhd", "")
        file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
        project.add_manual_dependency(file2, depends_on=file1)

        with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command:
            run_command.side_effect = iter([True, True])
            simif.compile_source_files(project)
            run_command.assert_has_calls([mock.call(["command1"]),
                                          mock.call(["command2"])])
        self.assertEqual(project.get_files_in_compile_order(incremental=True), [])

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_compile_project_verilog(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
        find_cds_root_irun.return_value = "cds_root_irun"
        find_cds_root_virtuoso.return_value = None
        simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.v", "")
        project.add_source_file("file.v", "lib", file_type="verilog")
        simif.compile_project(project)
        args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
        run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
        self.assertEqual(
            read_file(args_file).splitlines(),
            [
                "-compile",
                "-nocopyright",
                "-licqueue",
                "-nowarn UEXPSC",
                "-nowarn DLCPTH",
                "-nowarn DLCVAR",
                "-work work",
                '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
                "-quiet",
                '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
                '-nclibdirname ""',
                "-makelib lib",
                '"file.v"',
                "-endlib",
            ],
        )

        self.assertEqual(
            read_file(join(self.output_path, "cds.lib")),
            """\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
"""
            % self.output_path,
        )

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
    def test_add_source_file_has_vhdl_standard(self):
        write_file("file.vhd", "")

        for std in ('93', '2002', '2008'):
            project = Project()
            project.add_library("lib", "lib_path")
            source_file = project.add_source_file("file.vhd",
                                                  library_name="lib", file_type='vhdl', vhdl_standard=std)
            self.assertEqual(source_file.get_vhdl_standard(), std)

# 需要导入模块: from vunit.project import Project [as 别名]
# 或者: from vunit.project.Project import add_source_file [as 别名]
 def test_compile_project_verilog(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = ActiveHDLInterface(prefix="prefix",
                                library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog")
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
     run_command.assert_called_once_with([join('prefix', 'vlog'),
                                          '-quiet',
                                          '-sv2k12',
                                          '-lc',
                                          library_cfg,
                                          '-work',
                                          'lib',
                                          'file.v',
                                          '-l', 'lib'])