本文整理汇总了Python中myhdl.Signal.next方法的典型用法代码示例。如果您正苦于以下问题：Python Signal.next方法的具体用法？Python Signal.next怎么用？Python Signal.next使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类myhdl.Signal的用法示例。
在下文中一共展示了Signal.next方法的12个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: bench
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def bench(self):
clk = Signal(0)
sig1 = Signal(0)
sig2 = Signal(0)
td = 10
def gen(s, n):
for i in range(n-1):
yield delay(td)
s.next = 1
yield delay(td)
for i in range(10):
offset = now()
n0 = randrange(1, 50)
n1 = randrange(1, 50)
n2 = randrange(1, 50)
sig1.next = 0
sig2.next = 0
yield join(delay(n0*td), gen(sig1, n1), gen(sig2, n2))
assert sig1.val == 1
assert sig2.val == 1
assert now() == offset + td * max(n0, n1, n2)
raise StopSimulation("Joined concurrent generator yield")示例2: testSignalBoolBounds
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def testSignalBoolBounds(self):
if type(bool) is not type: # bool not a type in 2.2
return
s = Signal(bool())
s.next = 1
s.next = 0
for v in (-1, -8, 2, 5):
with pytest.raises(ValueError):
s.next = v示例3: inst
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def inst():
yield delay(200 * nsec)
addr = Signal(intbv(0x10)[len(bus.A):])
while 1:
yield system.CLK.posedge
bus.CS_B.next = 0
bus.RAS_B.next = 0
bus.A.next = 0x4
bus.BA.next = 0x2
yield system.CLK.posedge
bus.CS_B.next = 1
bus.RAS_B.next = 1
bus.A.next = ~0 & mask(bus.A)
bus.BA.next = ~0 & mask(bus.BA)
yield system.CLK.posedge
bus.CS_B.next = 0
bus.CAS_B.next = 0
bus.A.next = addr
bus.BA.next = 0
yield system.CLK.posedge
bus.CS_B.next = 1
bus.CAS_B.next = 1
bus.A.next = ~0 & mask(bus.A)
bus.BA.next = ~0 & mask(bus.BA)
addr.next = 0
if addr != n - 1:
addr.next = addr + 4
yield system.CLK.posedge
bus.CS_B.next = 0
bus.CAS_B.next = 0
bus.A.next = addr
yield system.CLK.posedge
bus.CS_B.next = 1
bus.CAS_B.next = 1
bus.A.next = ~0 & mask(bus.A)
addr.next = 0
if addr != n - 1:
addr.next = addr + 4
yield delay(interval - 1)示例4: testUpdateNoEvent
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def testUpdateNoEvent(self):
""" update without value change should not return event waiters """
s1 = Signal(1)
s1.next = 4
s1._update()
s1.next = 4
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
self.assertEqual(waiters, [])
self.assertEqual(s1._eventWaiters, self.eventWaiters)
self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)示例5: testSignalBoolBounds
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def testSignalBoolBounds(self):
if type(bool) is not type: # bool not a type in 2.2
return
s = Signal(bool())
s.next = 1
s.next = 0
for v in (-1, -8, 2, 5):
try:
s.next = v
#s._update()
#s.val
except ValueError:
pass
else:
self.fail()示例6: testUpdateEvent
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def testUpdateEvent(self):
""" update on non-edge event should return event waiters """
s1 = Signal(1)
s1.next = 4
s1._update()
s1.next = 5
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters
self.assertEqual(set(waiters), set(expected))
self.assertEqual(s1._eventWaiters, [])
self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)示例7: testUpdateNegedge
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def testUpdateNegedge(self):
""" update on negedge should return event and negedge waiters """
s1 = Signal(1)
s1.next = 1
s1._update()
s1.next = 0
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters + self.negedgeWaiters
self.assertEqual(set(waiters), set(expected))
self.assertEqual(s1._eventWaiters, [])
self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
self.assertEqual(s1._negedgeWaiters, [])示例8: testUpdatePosedge
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def testUpdatePosedge(self):
""" update on posedge should return event and posedge waiters """
s1 = Signal(1)
s1.next = 0
s1._update()
s1.next = 1
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters + self.posedgeWaiters
assert set(waiters) == set(expected)
assert s1._eventWaiters == []
assert s1._posedgeWaiters == []
assert s1._negedgeWaiters == self.negedgeWaiters示例9: stimulus
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def stimulus():
a = Signal(0)
yield delay(10)
a.next = 1
assert a.val == 0
assert now() == 10
yield None
a.next = 0
assert a.val == 0
assert now() == 10
yield None
a.next = 1
assert a.val == 0
assert now() == 10
yield delay(0)
assert a.val == 1
assert now() == 10示例10: stimulus
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def stimulus():
a = Signal(0)
yield delay(10)
a.next = 1
self.assertEqual(a.val, 0)
self.assertEqual(now(), 10)
yield None
a.next = 0
self.assertEqual(a.val, 0)
self.assertEqual(now(), 10)
yield None
a.next = 1
self.assertEqual(a.val, 0)
self.assertEqual(now(), 10)
yield delay(0)
self.assertEqual(a.val, 1)
self.assertEqual(now(), 10)示例11: stimulus
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def stimulus():
N = Signal(intbv(0)[32:])
yield bus.reset()
# Send a clear
yield whitebox_clear(bus)
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
yield bus.transmit(WE_THRESHOLD_ADDR,
concat(intbv(1)[16:], intbv(3)[16:]))
yield bus.receive(WE_THRESHOLD_ADDR)
assert bus.rdata == concat(intbv(1)[16:], intbv(3)[16:])
yield bus.transmit(WE_INTERP_ADDR, INTERP)
yield bus.receive(WE_INTERP_ADDR)
assert bus.rdata == INTERP
## Insert samples until overrun
yield bus.receive(WE_RUNS_ADDR)
while not (bus.rdata & 0x0000ffff):
x = intbv(int(sin(1000 * (2 * pi) * N / 50000) * 2**15), min=-2**15, max=2**15)[16:]
yield bus.transmit(WE_SAMPLE_ADDR, concat(x, x))
N.next = N + 1
yield bus.receive(WE_RUNS_ADDR)
# Check that we're full
yield bus.receive(WE_STATUS_ADDR)
assert not (bus.rdata & WES_SPACE)
assert bus.rdata & WES_DATA
## Now start transmitting
yield bus.transmit(WE_STATUS_ADDR, WES_TXEN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_TXEN
## Wait until underrun
yield bus.receive(WE_RUNS_ADDR)
while not (bus.rdata & 0xffff0000):
yield bus.delay(1000)
yield bus.receive(WE_RUNS_ADDR)
## Make sure we're both over and underrun
assert bus.rdata & 0xffff0000 and bus.rdata & 0x0000ffff
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
raise StopSimulation示例12: test
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import next [as 别名]
def test(B, G):
w = len(B)
G_Z = Signal(intbv(0)[w:])
B.next = intbv(0)
yield delay(10)
for i in range(1, 2**w):
G_Z.next = G
B.next = intbv(i)
yield delay(10)
diffcode = bin(G ^ G_Z)
self.assertEqual(diffcode.count('1'), 1)