本文整理汇总了Python中myhdl.Signal._name方法的典型用法代码示例。如果您正苦于以下问题：Python Signal._name方法的具体用法？Python Signal._name怎么用？Python Signal._name使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类myhdl.Signal的用法示例。
在下文中一共展示了Signal._name方法的1个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: top
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import _name [as 别名]
def top(din, init_b, cclk,
ref_clk,
soc_clk_p, soc_clk_n, soc_cs, soc_ras, soc_cas, soc_we, soc_ba, soc_a,
soc_dqs, soc_dm, soc_dq,
adc_clk_p, adc_clk_n, adc_dat_p, adc_dat_n, adc_ovr_p, adc_ovr_n,
shifter_sck, shifter_sdo,
bu2506_ld, adf4360_le, adc08d500_cs, lmh6518_cs, dac8532_sync,
trig_p, trig_n, ba7406_vd, ba7406_hd, ac_trig,
probe_comp, ext_trig_out,
i2c_scl, i2c_sda,
mcb3_dram_ck, mcb3_dram_ck_n,
mcb3_dram_ras_n, mcb3_dram_cas_n, mcb3_dram_we_n,
mcb3_dram_ba, mcb3_dram_a, mcb3_dram_odt,
mcb3_dram_dqs, mcb3_dram_dqs_n, mcb3_dram_udqs, mcb3_dram_udqs_n, mcb3_dram_dm, mcb3_dram_udm,
mcb3_dram_dq,
bank2):
insts = []
# Clock generator using STARTUP_SPARTAN primitive
clk_unbuf = Signal(False)
clk_unbuf_inst = startup_spartan6('startup_inst', cfgmclk = clk_unbuf)
insts.append(clk_unbuf_inst)
clk_buf = Signal(False)
clk_inst = bufg('bufg_clk', clk_unbuf, clk_buf)
insts.append(clk_inst)
system = System(clk_buf, None)
mux = WbMux()
# Rename and adapt external SPI bus signals
slave_spi_bus = SpiInterface()
slave_cs = Signal(False)
slave_cs_inst = syncro(clk_buf, din, slave_spi_bus.CS)
insts.append(slave_cs_inst)
slave_sck_inst = syncro(clk_buf, cclk, slave_spi_bus.SCK)
insts.append(slave_sck_inst)
slave_sdioinst = tristate(init_b,
slave_spi_bus.SD_I,
slave_spi_bus.SD_O, slave_spi_bus.SD_OE)
insts.append(slave_sdioinst)
####################################################################
# SoC bus
if 0:
soc_clk = Signal(False)
soc_clk_b = Signal(False)
soc_clk_inst = ibufgds_diff_out('ibufgds_diff_out_soc_clk', soc_clk_p, soc_clk_n, soc_clk, soc_clk_b)
insts.append(soc_clk_inst)
soc_clk._name = 'soc_clk' # Must match name of timing spec in ucf file
soc_clk_b._name = 'soc_clk_b' # Must match name of timing spec in ucf file
soc_system = System(soc_clk, None)
soc_bus = DdrBus(2, 12, 2)
soc_connect_inst = ddr_connect(
soc_bus, soc_clk, soc_clk_b, None,
soc_cs, soc_ras, soc_cas, soc_we, soc_ba, soc_a,
soc_dqs, soc_dm, soc_dq)
insts.append(soc_connect_inst)
if 1:
soc_source0 = DdrSource(soc_system, 16, 16)
soc_source1 = DdrSource(soc_system, 16, 16)
soc_ddr = Ddr(soc_source0, soc_source1)
soc_inst = soc_ddr.gen(soc_system, soc_bus)
insts.append(soc_inst)
if 1:
# Trace soc bus control signals
soc_capture = Signal(False)
soc_ctl = RegFile('soc_ctl', "SOC control", [
RwField(system, 'soc_capture', "Capture samples", soc_capture),
])
mux.add(soc_ctl, 0x231)
soc_capture_sync = Signal(False)
soc_capture_sync_inst = syncro(soc_clk, soc_capture, soc_capture_sync)
insts.append(soc_capture_sync_inst)
soc_sdr = ConcatSignal(
soc_a, soc_ba, soc_we, soc_cas, soc_ras, soc_cs)
soc_sdr_sampler = Sampler(addr_depth = 0x800,
sample_clk = soc_clk,
sample_data = soc_sdr,
sample_enable = soc_capture_sync)
mux.add(soc_sdr_sampler, 0x2000)
soc_reg = ConcatSignal(
soc_bus.A, soc_bus.BA,
soc_bus.WE_B, soc_bus.CAS_B, soc_bus.RAS_B, soc_bus.CS_B)
soc_reg_sampler = Sampler(addr_depth = 0x800,
sample_clk = soc_clk,
#.........这里部分代码省略.........