本文整理汇总了Python中myhdl.Signal.driven方法的典型用法代码示例。如果您正苦于以下问题：Python Signal.driven方法的具体用法？Python Signal.driven怎么用？Python Signal.driven使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类myhdl.Signal的用法示例。
在下文中一共展示了Signal.driven方法的6个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: assign_config
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import driven [as 别名]
def assign_config(sig, val):
keep = Signal(bool(0))
keep.driven = 'wire'
@always_comb
def beh_assign():
sig.next = val if keep else val
return beh_assign示例2: testDrivenAttrValue
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import driven [as 别名]
def testDrivenAttrValue(self):
""" driven attribute only accepts value 'reg' or 'wire' """
s1 = Signal(1)
try:
s1.driven = "signal"
except ValueError:
pass
else:
self.fail()示例3: assign_config
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import driven [as 别名]
def assign_config(sig, val):
"""
Arguments:
sig (Signal): The signals to be assigned to a constant value
val (int): The constant value
"""
keep = Signal(bool(0))
keep.driven = 'wire'
@always_comb
def beh_assign():
sig.next = val if keep else val
return beh_assign示例4: assign
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import driven [as 别名]
def assign(a, b):
""" assign a = b
"""
if isinstance(b, SignalType):
@always_comb
def beh_assign():
a.next = b
else:
# this is a work around for preserving constant assigns
keep = Signal(True)
keep.driven = "wire"
@always_comb
def beh_assign():
a.next = b if keep else b
return beh_assign示例5: exciter
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import driven [as 别名]
def exciter(
resetn,
system_clock,
pclk,
paddr,
psel,
penable,
pwrite,
pwdata,
pready,
prdata,
pslverr,
dac_clock,
dac_data):
####### FIFO ############
# Read
re = Signal(bool(False))
rclk = system_clock
Q = Signal(intbv(0)[32:])
# Write
we = Signal(bool(False))
wclk = pclk
data = Signal(intbv(0)[32:])
# Threshold
full = Signal(bool(False))
full.driven = 'wire'
afull = Signal(bool(False))
afull.driven = 'wire'
empty = Signal(bool(False))
empty.driven = 'wire'
aempty = Signal(bool(False))
aempty.driven = 'wire'
fifo_args = resetn, re, rclk, Q, we, wclk, data, full, afull, \
empty, aempty
fifo = FIFO(*fifo_args,
width=32,
depth=1024)
######### RESAMPLER ###########
######### INTERLEAVER #########
in_phase = Signal(bool(0))
sample_i = Signal(intbv(0, 0, 2**10))
sample_q = Signal(intbv(0, 0, 2**10))
########## STATE MACHINE ######
state_t = enum('IDLE', 'WRITE_SAMPLE', 'DONE',)
state = Signal(state_t.IDLE)
############ TX EN ###########
txen = Signal(bool(0))
@always_seq(pclk.posedge, reset=resetn)
def state_machine():
if state == state_t.IDLE:
if penable and psel and pwrite:
if paddr[8:] == 0x00:
state.next = state_t.WRITE_SAMPLE
pready.next = 0
we.next = 1
data.next = pwdata
if full:
raise OverrunError
elif paddr[8:] == 0x01:
print 'hi', pwdata
txen.next = pwdata[0]
elif psel and not pwrite:
pass
elif state == state_t.WRITE_SAMPLE:
we.next = 0
state.next = state_t.DONE
elif state == state_t.DONE:
pready.next = 1
state.next = state_t.IDLE
@always(system_clock.posedge)
def resampler():
if txen: # Update the sample out of phase, locking
if re:
sample_i.next = Q[9:]
sample_q.next = Q[32:23]
re.next = not re
@always(system_clock.posedge)
def interleaver():
if txen:
dac_data.next = sample_i[10:2] if in_phase else sample_q[10:2]
dac_clock.next = not in_phase
in_phase.next = not in_phase
return fifo, state_machine, resampler, interleaver示例6: testDrivenAttrValue
# 需要导入模块: from myhdl import Signal [as 别名]
# 或者: from myhdl.Signal import driven [as 别名]
def testDrivenAttrValue(self):
""" driven attribute only accepts value 'reg' or 'wire' """
s1 = Signal(1)
with pytest.raises(ValueError):
s1.driven = "signal"