Python Dut.init方法代码示例

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestSimGpio(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([os.getcwd() + '/test_SimGpio.v'])

        self.chip = Dut(cnfg_yaml)
        self.chip.init()

    def test_io(self):
        ret = self.chip['gpio'].get_data()
        self.assertEqual([0, 0, 0], ret)

        self.chip['gpio'].set_data([0xe3, 0xfa, 0x5a])
        ret = self.chip['gpio'].get_data()
        self.assertEqual([0, 0x5a, 0x5a], ret)

        self.chip['gpio'].set_output_en([0x0f, 0, 0])
        ret = self.chip['gpio'].get_data()
        self.assertEqual([0x33, 0x5a, 0x5a], ret)

    def test_io_register(self):
        self.chip['GPIO']['OUT'] = 0xa5
        self.chip['GPIO'].write()
        ret = self.chip['gpio'].get_data()
        self.assertEqual([0, 0xa5, 0xa5], ret)
        # TODO: Add register readback and comparison

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestSimS2C(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([os.path.dirname(__file__) + '/test_SimI2c.v'])

        self.chip = Dut(cnfg_yaml)
        self.chip.init()

    def test_i2c(self):
        data = [0x85, 0x81, 0xa5, 0x91]
        self.chip['i2c'].write(0x92, data)

        ret = self.chip['i2c'].get_data(4)
        self.assertEqual(ret.tolist(), data)

        self.chip['i2c'].write(0x92, data[0:1])

        self.chip['i2c'].set_data([0, 1, 2, 3])

        ret = self.chip['i2c'].read(0x92, 3)
        self.assertEqual(ret.tolist(), data[1:])

        # no ack/no such device
        exept = False
        try:
            self.chip['i2c'].write(0x55, data)
        except IOError:
            exept = True

        self.assertEqual(exept, True)

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestExampleMIO(unittest.TestCase):
    def setUp(self):

        fw_path = get_basil_dir() + "/firmware/modules"
        cocotb_compile_and_run(
            [
                fw_path + "/gpio/gpio.v",
                fw_path + "/utils/reset_gen.v",
                fw_path + "/utils/bus_to_ip.v",
                fw_path + "/utils/fx2_to_bus.v",
                os.path.dirname(__file__) + "/../src/example.v",
            ],
            top_level="example",
            sim_bus="basil.utils.sim.SiLibUsbBusDriver",
        )

        with open(os.path.dirname(__file__) + "/example.yaml", "r") as f:
            cnfg = yaml.load(f)

        # change to simulation interface
        cnfg["transfer_layer"][0]["type"] = "SiSim"

        self.chip = Dut(cnfg)
        self.chip.init()

    def test(self):

        ret = self.chip["GPIO_LED"].get_data()
        self.assertEqual([0], ret)

        self.chip["GPIO_LED"]["LED"] = 0x01
        self.chip["GPIO_LED"].write()

        ret = self.chip["GPIO_LED"].get_data()
        self.assertEqual([0x21], ret)

        self.chip["GPIO_LED"]["LED"] = 0x02
        self.chip["GPIO_LED"].write()

        ret = self.chip["GPIO_LED"].get_data()
        self.assertEqual([0x42], ret)

        self.chip["GPIO_LED"]["LED"] = 0x03
        self.chip["GPIO_LED"].write()

        ret = self.chip["GPIO_LED"].get_data()
        self.assertEqual([0x63], ret)

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestExampleMIO(unittest.TestCase):
    def setUp(self):
        fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
        cocotb_compile_and_run([
            os.path.join(fw_path, 'gpio/gpio.v'),
            os.path.join(fw_path, 'utils/reset_gen.v'),
            os.path.join(fw_path, 'utils/bus_to_ip.v'),
            os.path.join(fw_path, 'utils/fx2_to_bus.v'),
            os.path.join(os.path.dirname(__file__), '../src/example.v')],
            top_level='example',
            sim_bus='basil.utils.sim.SiLibUsbBusDriver'
        )

        with open(os.path.join(os.path.dirname(__file__), 'example.yaml'), 'r') as f:
            cnfg = yaml.load(f)

        # change to simulation interface
        cnfg['transfer_layer'][0]['type'] = 'SiSim'

        self.chip = Dut(cnfg)
        self.chip.init()

    def test_gpio(self):
        ret = self.chip['GPIO_LED'].get_data()
        self.assertEqual([0], ret)

        self.chip['GPIO_LED']['LED'] = 0x01
        self.chip['GPIO_LED'].write()

        ret = self.chip['GPIO_LED'].get_data()
        self.assertEqual([0x21], ret)

        self.chip['GPIO_LED']['LED'] = 0x02
        self.chip['GPIO_LED'].write()

        ret = self.chip['GPIO_LED'].get_data()
        self.assertEqual([0x42], ret)

        self.chip['GPIO_LED']['LED'] = 0x03
        self.chip['GPIO_LED'].write()

        ret = self.chip['GPIO_LED'].get_data()
        self.assertEqual([0x63], ret)

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class Silab_relay(object):
    def __init__(self, yaml='relay.yaml'):
        self.dut = Dut(yaml)
        self.dut.init()
        time.sleep(1)
    
    def switch(self, channel, state='toggle'):
        '''
        Sets one channel of relay card to defined state or toggles
        '''
        if channel == 'All' or channel == 'all' or channel == 99:
            send_channel = 99
        elif type(channel) == int and channel >= 0 and channel <= 9:
            send_channel = channel + 2
        else:
            raise ValueError('Channel has to be integer between 0 and 9 or String \'All\'.')
            
        if state == 'On' or state == 'on' or state == 1 or state == True:
            send_state = 1
        elif state == 'Off' or state == 'off' or state == 0 or state == False:
            send_state = 0
        elif state == 'toggle' or state == 'Toggle':
            send_state = 0 if bool(self.get_state(channel)) else 1
            print send_state
            raise NotImplementedError
        else:
            raise ValueError('State has to be either 1/0 or \'On\'/\'Off\' or True/False.')
        
        self.dut['Arduino'].set_output(channel=send_channel, value=send_state)
    
    def switch_to(self, channel):
        self.switch('all', 'off')
        self.switch(channel, 'on')
        
    def get_state(self, channel='all'):
        '''
        Will only work as long as connection is open. On reconnect, the arduino resets and sets all pins to LOW.
        '''
        state = self.dut['Arduino'].get_state()

        if channel == 'all' or channel == 'All' or channel == 99:
            return state
        elif type(channel) == int and channel >= 0 and channel <= 9:
            return state[channel]
        else:
            raise ValueError('Channel has to be integer between 0 and 9 or String \'All\'.')

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestSimGpio(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([os.getcwd() + '/test_SimAdcRx.v'])

        self.chip = Dut(cnfg_yaml)
        self.chip.init()

    def test_io(self):
        pattern = [1, 0, 1, 1, 1, 2, 1, 3, 1, 4, 1, 5, 1, 6, 1, 7]
        self.chip['SEQ_GEN'].set_data(pattern)

        self.chip['PULSE_GEN'].set_delay(1)
        self.chip['PULSE_GEN'].set_width(1)

        self.chip['SEQ_GEN'].set_en_ext_start(True)
        self.chip['SEQ_GEN'].set_size(8)
        self.chip['SEQ_GEN'].set_repeat(1)

        # this is to have something in memory and not X
        self.chip['PULSE_GEN'].start()
        self.chip['SEQ_GEN'].is_done()
        self.chip['SEQ_GEN'].is_done()

        while(not self.chip['SEQ_GEN'].is_done()):
            pass

        # take some data
        self.chip['FADC'].set_align_to_sync(True)
        self.chip['FADC'].set_data_count(16)
        self.chip['FADC'].set_single_data(True)
        self.chip['FADC'].start()

        self.chip['PULSE_GEN'].start()
        self.chip['SEQ_GEN'].is_done()
        self.chip['SEQ_GEN'].is_done()

        while(not self.chip['FADC'].is_done()):
            pass

        ret = self.chip['fifo'].get_data()
        self.assertEqual(ret[2:2 + 8].tolist(), [0x0100, 0x0101, 0x0102, 0x0103, 0x0104, 0x0105, 0x0106, 0x0107])

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestSimScpi(unittest.TestCase):

    def setUp(self):
        cfg = yaml.load(cnfg_yaml)
        self.device = Dut(cfg)
        self.device.init()

    def test_read(self):
        self.assertEqual(self.device['Pulser'].get_frequency(), u'100.00')

    def test_write(self):
        self.device['Pulser'].set_on()
        self.assertEqual(self.device['Pulser'].get_on(), u'0')

    def test_exception(self):
        with self.assertRaises(ValueError):
            self.device['Pulser'].unknown_function()

    def tearDown(self):
        self.device.close()

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
    def scan(self, pix_list=((6, 20),), mask_steps=4, repeat_command=101, columns=[True] * 16, scan_range=[0, 1.2, 0.1],
             vthin1Dac=80, vthin2Dac=0, PrmpVbpDac=80, preCompVbnDac=50, mask_filename='', **kwargs):
        '''Scan loop
        This scan is to measure time walk. The charge injection can be driven by the GPAC or an external device.
        In the latter case the device is Agilent 33250a connected through serial port.
        The time walk and TOT are measured by a TDC module in the FPGA.
        The output is an .h5 file (data) and an .html file with plots.

        Parameters
        ----------
        mask : int
            Number of mask steps.
        repeat : int
            Number of injections.
        '''
        inj_factor = 1.0
        INJ_LO = 0.0
        try:
            dut = Dut(ScanBase.get_basil_dir(self) + '/examples/lab_devices/agilent33250a_pyserial.yaml')
            dut.init()
            logging.info('Connected to ' + str(dut['Pulser'].get_info()))
        except RuntimeError:
            INJ_LO = 0.2
            inj_factor = 2.0
            logging.info('External injector not connected. Switch to internal one')
            self.dut['INJ_LO'].set_voltage(INJ_LO, unit='V')

        self.dut['global_conf']['PrmpVbpDac'] = 80
        #        self.dut['global_conf']['vthin1Dac'] = 255
        self.dut['global_conf']['vthin2Dac'] = 0
        self.dut['global_conf']['vffDac'] = 24
        self.dut['global_conf']['PrmpVbnFolDac'] = 51
        self.dut['global_conf']['vbnLccDac'] = 1
        self.dut['global_conf']['compVbnDac'] = 25
        self.dut['global_conf']['preCompVbnDac'] = 110  # 50

        self.dut.write_global()
        self.dut['control']['RESET'] = 0b01
        self.dut['control']['DISABLE_LD'] = 0
        self.dut['control']['PIX_D_CONF'] = 0
        self.dut['control'].write()

        self.dut['control']['CLK_OUT_GATE'] = 1
        self.dut['control']['CLK_BX_GATE'] = 1
        self.dut['control'].write()
        time.sleep(0.1)

        self.dut['control']['RESET'] = 0b11
        self.dut['control'].write()

        self.dut['global_conf']['OneSr'] = 1

        self.dut['global_conf']['TestHit'] = 0
        self.dut['global_conf']['SignLd'] = 0
        self.dut['global_conf']['InjEnLd'] = 0
        self.dut['global_conf']['TDacLd'] = 0
        self.dut['global_conf']['PixConfLd'] = 0
        self.dut.write_global()

        self.dut['global_conf']['ColEn'][:] = bitarray.bitarray([True] * 16)  # (columns)
        self.dut['global_conf']['ColSrEn'][:] = bitarray.bitarray([True] * 16)
        self.dut.write_global()

        self.dut['pixel_conf'].setall(False)
        self.dut.write_pixel()
        self.dut['global_conf']['InjEnLd'] = 1
        self.dut.write_global()
        self.dut['global_conf']['InjEnLd'] = 0

        mask_en = np.full([64, 64], False, dtype=np.bool)
        mask_tdac = np.full([64, 64], 16, dtype=np.uint8)

        for inx, col in enumerate(columns):
            if col:
                mask_en[inx * 4:(inx + 1) * 4, :] = True

        if mask_filename:
            logging.info('Using pixel mask from file: %s', mask_filename)

            with tb.open_file(mask_filename, 'r') as in_file_h5:
                mask_tdac = in_file_h5.root.scan_results.tdac_mask[:]
                mask_en = in_file_h5.root.scan_results.en_mask[:]

        self.dut.write_en_mask(mask_en)
        self.dut.write_tune_mask(mask_tdac)

        self.dut['global_conf']['OneSr'] = 1
        self.dut.write_global()

        self.dut['inj'].set_delay(50000)  # 1 zero more
        self.dut['inj'].set_width(1000)
        self.dut['inj'].set_repeat(repeat_command)
        self.dut['inj'].set_en(False)

        self.dut['trigger'].set_delay(400 - 4)
        self.dut['trigger'].set_width(16)
        self.dut['trigger'].set_repeat(1)
        self.dut['trigger'].set_en(False)

        logging.debug('Enable TDC')
#.........这里部分代码省略.........

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestSimSpi(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([os.getcwd() + '/test_SimSpi.v'])

        self.chip = Dut(cnfg_yaml)
        self.chip.init()
    
    def test_io(self):
        size = self.chip['spi'].get_size()
        self.chip['gpio'].reset()
        self.assertEqual(size, 16 * 8)

        self.chip['spi'].set_data(range(16))
        ret = self.chip['spi'].get_data(size=16, addr=0)  # to read back what was written
        self.assertEqual(ret.tolist(), range(16))

        self.chip['spi'].set_data(range(16))
        ret = self.chip['spi'].get_data(addr=0)  # to read back what was written
        self.assertEqual(ret.tolist(), range(16))

        self.chip['spi'].start()
        while(not self.chip['spi'].is_done()):
            pass

        ret = self.chip['spi'].get_data()  # read back what was received (looped)
        self.assertEqual(ret.tolist(), range(16))
        
        # ext_start
        self.chip['spi'].set_en(1)
        self.assertEqual(self.chip['spi'].get_en(), 1)
        
        self.chip['PULSE_GEN'].set_delay(1)
        self.chip['PULSE_GEN'].set_width(1+size)
        self.chip['PULSE_GEN'].set_repeat(1)
        self.assertEqual(self.chip['PULSE_GEN'].get_delay(), 1)
        self.assertEqual(self.chip['PULSE_GEN'].get_width(), 1+size)
        self.assertEqual(self.chip['PULSE_GEN'].get_repeat(), 1)
        
        self.chip['PULSE_GEN'].start()
        while(not self.chip['PULSE_GEN'].is_done()):
            pass
            
        ret = self.chip['spi'].get_data()  # read back what was received (looped)
        self.assertEqual(ret.tolist(), range(16))
        
        # spi_rx
        ret = self.chip['spi_rx'].get_en()
        self.assertEqual(ret, False)

        self.chip['spi_rx'].set_en(True)
        ret = self.chip['spi_rx'].get_en()
        self.assertEqual(ret, True)

        self.chip['spi'].start()
        while(not self.chip['spi'].is_done()):
            pass

        ret = self.chip['fifo'].get_fifo_size()
        self.assertEqual(ret, 32)

        ret = self.chip['fifo'].get_data()

        data0 = ret.astype(np.uint8)
        data1 = np.right_shift(ret, 8).astype(np.uint8)
        data = np.reshape(np.vstack((data1, data0)), -1, order='F')
        self.assertEqual(data.tolist(), range(16))
    
    def test_dut_iter(self):
        
        conf = yaml.safe_load(cnfg_yaml)
        def iter_conf():
            for item in conf['registers']:
                yield item
            for item in conf['hw_drivers']:
                yield item
            for item in conf['transfer_layer']:
                yield item
            
        
        for mod, mcnf in zip(self.chip, iter_conf()):
            self.assertEqual(mod.name, mcnf['name'])
            self.assertEqual(mod.__class__.__name__, mcnf['type'])
    
    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestSimJtagGpio(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([
            os.path.join(os.path.dirname(__file__), 'jtag_tap.v'),
            os.path.join(os.path.dirname(__file__), 'test_SimJtagGpio.v')]
        )

        self.chip = Dut(cnfg_yaml)
        self.chip.init(init_yaml)

    def test_gpio(self):

        ID_CODE = BitLogic('0010')
        BYPASS = BitLogic('1111')
        DEBUG = BitLogic('1000')

        ret_ir = BitLogic('0101')

        # TEST REG INIT
        dev1ret = StdRegister(driver=None, conf=yaml.load(gpio_yaml))
        dev1ret.init()
        dev1ret['F1'] = 0x1
        dev1ret['F2'] = 0x2f
        dev1ret['F3'] = 0x2
        dev1ret['F4'] = 0x17cf4
        self.assertEqual(dev1ret[:], self.chip['DEV1'][:])

        self.chip['DEV1']['F2'] = 0
        self.assertFalse(dev1ret[:] == self.chip['DEV1'][:])

        self.chip.set_configuration(init_yaml)
        self.assertEqual(dev1ret[:], self.chip['DEV1'][:])

        self.chip['jtag'].reset()

        # IR CODE
        ret = self.chip['jtag'].scan_ir([ID_CODE] * 2)
        self.assertEqual(ret, [ret_ir] * 2)

        # ID CODE
        id_code = BitLogic.from_value(0x149B51C3, fmt='I')
        ret = self.chip['jtag'].scan_dr(['0' * 32] * 2)
        self.assertEqual(ret, [id_code] * 2)

        # BYPASS + ID CODE
        bypass_code = BitLogic('0')
        ret = self.chip['jtag'].scan_ir([ID_CODE, BYPASS])
        self.assertEqual(ret, [ret_ir] * 2)
        ret = self.chip['jtag'].scan_dr(['0' * 32, '1'])
        self.assertEqual(ret, [id_code, bypass_code])

        ret = self.chip['jtag'].scan_ir([BYPASS, ID_CODE])
        self.assertEqual(ret, [ret_ir] * 2)
        ret = self.chip['jtag'].scan_dr(['1', '0' * 32])
        self.assertEqual(ret, [bypass_code, id_code])

        # DEBUG
        ret = self.chip['jtag'].scan_ir([DEBUG, DEBUG])
        self.assertEqual(ret, [ret_ir] * 2)

        self.chip['jtag'].scan_dr(['1' * 32, '0' * 1 + '1' * 30 + '0' * 1])
        ret = self.chip['jtag'].scan_dr(['0' * 32, '1' * 32])
        self.assertEqual(ret, [BitLogic('1' * 32), BitLogic('0' * 1 + '1' * 30 + '0' * 1)])
        ret = self.chip['jtag'].scan_dr(['0' * 32, '0' * 32])
        self.assertEqual(ret, [BitLogic('0' * 32), BitLogic('1' * 32)])

        # SHIT IN DEV REG/DEBUG
        self.chip['jtag'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])

        # GPIO RETURN
        dev1ret.frombytes(self.chip['gpio_dev1'].get_data())
        self.assertEqual(dev1ret[:], self.chip['DEV1'][:])

        self.assertFalse(dev1ret[:] == self.chip['DEV2'][:])
        dev1ret.frombytes(self.chip['gpio_dev2'].get_data())
        self.assertEqual(dev1ret[:], self.chip['DEV2'][:])

        # JTAG RETURN
        ret = self.chip['jtag'].scan_dr(['0' * 32, '0' * 32])
        dev1ret.set(ret[0])
        self.assertEqual(dev1ret[:], self.chip['DEV1'][:])

        dev1ret.set(ret[1])
        self.assertEqual(dev1ret[:], self.chip['DEV2'][:])

        # REPEATING REGISTER
        self.chip['jtag'].scan_dr([self.chip['DEV'][:]])
        ret1 = self.chip['jtag'].scan_dr([self.chip['DEV'][:]])
        self.chip['jtag'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
        ret2 = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
        ret3 = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
        self.assertEqual(ret1[:], ret2[:])
        self.assertEqual(ret2[:], ret3[:])

        # REPEATING SETTING
        self.chip['jtag'].scan_dr(['1' * 32 + '0' * 32])
        ret = self.chip['jtag'].scan_dr(['0' * 32 + '0' * 32])

        self.chip['DEV'].set(ret[0])
        self.assertEqual(self.chip['DEV'][:], BitLogic('0' * 32 + '1' * 32))
#.........这里部分代码省略.........

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestSram(unittest.TestCase):
    def setUp(self):

        fw_path = get_basil_dir() + "/firmware/modules"
        cocotb_compile_and_run(
            [
                fw_path + "/gpio/gpio.v",
                fw_path + "/utils/reset_gen.v",
                fw_path + "/utils/bus_to_ip.v",
                fw_path + "/rrp_arbiter/rrp_arbiter.v",
                fw_path + "/utils/ODDR_sim.v",
                fw_path + "/utils/generic_fifo.v",
                fw_path + "/utils/cdc_pulse_sync.v",
                fw_path + "/utils/fx2_to_bus.v",
                fw_path + "/pulse_gen/pulse_gen.v",
                fw_path + "/pulse_gen/pulse_gen_core.v",
                fw_path + "/sram_fifo/sram_fifo_core.v",
                fw_path + "/sram_fifo/sram_fifo.v",
                os.path.dirname(__file__) + "/../firmware/src/sram_test.v",
                os.path.dirname(__file__) + "/../tests/tb.v",
            ],
            top_level="tb",
            sim_bus="basil.utils.sim.SiLibUsbBusDriver",
        )

        with open(os.path.dirname(__file__) + "/../sram_test.yaml", "r") as f:
            cnfg = yaml.load(f)

        # change to simulation interface
        cnfg["transfer_layer"][0]["type"] = "SiSim"

        self.chip = Dut(cnfg)
        self.chip.init()

    def test_simple(self):
        self.chip["CONTROL"]["COUNTER_EN"] = 1
        self.chip["CONTROL"].write()
        self.chip["CONTROL"].write()
        self.chip["CONTROL"]["COUNTER_EN"] = 0
        self.chip["CONTROL"].write()
        for _ in range(10):
            self.chip["CONTROL"].write()

        ret = self.chip["fifo"].get_data()

        self.chip["CONTROL"]["COUNTER_EN"] = 1
        self.chip["CONTROL"].write()
        self.chip["CONTROL"].write()
        self.chip["CONTROL"].write()
        self.chip["CONTROL"]["COUNTER_EN"] = 0
        for _ in range(10):
            self.chip["CONTROL"].write()

        ret = np.hstack((ret, self.chip["fifo"].get_data()))

        x = np.arange(175 * 4, dtype=np.uint8)
        x.dtype = np.uint32

        self.assertTrue(np.alltrue(ret == x))

        self.chip["fifo"].reset()

        self.chip["CONTROL"]["COUNTER_EN"] = 1
        self.chip["CONTROL"].write()
        self.chip["CONTROL"].write()

        self.chip["CONTROL"]["COUNTER_EN"] = 0
        self.chip["CONTROL"].write()
        self.chip["CONTROL"].write()
        self.chip["CONTROL"].write()

        ret = np.hstack((ret, self.chip["fifo"].get_data()))

        x = np.arange(245 * 4, dtype=np.uint8)
        x.dtype = np.uint32

        self.assertEqual(ret.tolist(), x.tolist())

    def test_full(self):
        self.chip["CONTROL"]["COUNTER_EN"] = 1
        self.chip["CONTROL"].write()

        for _ in range(2):
            self.chip["fifo"].get_fifo_size()

        self.chip["CONTROL"]["COUNTER_EN"] = 0
        self.chip["CONTROL"].write()

        for _ in range(10):
            self.chip["CONTROL"].write()

        size = self.chip["fifo"].get_fifo_size()
        self.assertEqual(size, 512)

        ret = self.chip["fifo"].get_data()
        ret = np.hstack((ret, self.chip["fifo"].get_data()))

        x = np.arange(203 * 4, dtype=np.uint8)
        x.dtype = np.uint32

#.........这里部分代码省略.........

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
class TestSimSeq(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([os.getcwd() + '/test_SimSeq.v'])

        self.chip = Dut(cnfg_yaml)
        self.chip.init()

    def test_io(self):
        self.assertEqual(self.chip['SEQ_GEN'].get_mem_size(), 8 * 1024)

        self.chip['SEQ']['S0'][0] = 1
        self.chip['SEQ']['S1'][1] = 1
        self.chip['SEQ']['S2'][2] = 1
        self.chip['SEQ']['S3'][3] = 1

        self.chip['SEQ']['S4'][12] = 1
        self.chip['SEQ']['S5'][13] = 1
        self.chip['SEQ']['S6'][14] = 1
        self.chip['SEQ']['S7'][15] = 1

        pattern = [0x01, 0x02, 0x04, 0x08, 0, 0, 0, 0, 0, 0, 0, 0, 0x10, 0x20, 0x40, 0x80]

        self.chip['SEQ'].write(16)

        ret = self.chip['SEQ'].get_data(size=16)
        self.assertEqual(ret.tolist(), pattern)

        rec_size = 16 * 4 + 8
        self.chip['SEQ_REC'].set_en_ext_start(True)
        self.chip['SEQ_REC'].set_size(rec_size)

        self.chip['PULSE_GEN'].set_delay(1)
        self.chip['PULSE_GEN'].set_width(1)

        self.assertEqual(self.chip['PULSE_GEN'].get_delay(), 1)
        self.assertEqual(self.chip['PULSE_GEN'].get_width(), 1)

        self.chip['SEQ'].set_repeat(4)
        self.chip['SEQ'].set_en_ext_start(True)
        self.chip['SEQ'].set_size(16)
        # self.chip['SEQ'].start()

        self.chip['PULSE_GEN'].start()

        while(not self.chip['SEQ'].is_done()):
            pass

        ret = self.chip['SEQ_REC'].get_data(size=rec_size)
        self.assertEqual(ret.tolist(), [0x0] * 2 + pattern * 4 + [0x80] * 6)  # 2 clk delay + pattern x4 + 6 x last pattern

        #
        self.chip['SEQ'].set_repeat_start(12)
        self.chip['PULSE_GEN'].start()

        while(not self.chip['SEQ'].is_done()):
            pass

        ret = self.chip['SEQ_REC'].get_data(size=rec_size)
        self.assertEqual(ret.tolist(), [0x80] * 2 + pattern + pattern[12:] * 3 + [0x80] * 3 * 12 + [0x80] * 6)  # 2 clk delay 0x80 > from last pattern + ...

        self.chip['SEQ'].set_wait(4)
        self.chip['PULSE_GEN'].start()

        while(not self.chip['SEQ'].is_done()):
            pass

        ret = self.chip['SEQ_REC'].get_data(size=rec_size)
        lpat = pattern[12:] + [0x80] * 4
        self.assertEqual(ret.tolist(), [0x80] * 2 + pattern + [0x80] * 4 + lpat * 3 + [0x80] * (3 * 12 - 4 * 4) + [0x80] * 6)

        #
        rec_size = rec_size * 3
        self.chip['SEQ_REC'].set_size(rec_size)
        self.chip['SEQ'].set_clk_divide(3)
        self.chip['SEQ'].set_wait(3)
        self.chip['PULSE_GEN'].start()

        while(not self.chip['SEQ'].is_done()):
            pass

        ret = self.chip['SEQ_REC'].get_data(size=rec_size)
        lpat = pattern[12:] + [0x80] * 3
        mu_pat = pattern + [0x80] * 3 + lpat * 3
        fm = []
        for i in mu_pat:
            fm += [i, i, i]
        self.assertEqual(ret.tolist(), [0x80] * 2 + fm + [0x80] * 94)

        #
        self.chip['SEQ'].set_wait(0)
        self.chip['PULSE_GEN'].start()

        while(not self.chip['SEQ'].is_done()):
            pass

        ret = self.chip['SEQ_REC'].get_data(size=rec_size)
        lpat = pattern[12:]
        mu_pat = pattern + lpat * 3
        fm = []
        for i in mu_pat:
#.........这里部分代码省略.........

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
    def scan(self, mask_steps=4, repeat_command=100, PrmpVbpDac=80, vthin2Dac=0, columns = [True] * 16, scan_range = [0, 0.2, 0.005], vthin1Dac = 80, preCompVbnDac = 50, mask_filename='', **kwargs):

        '''Scan loop
        Parameters
        ----------
        mask : int
            Number of mask steps.
        repeat : int
            Number of injections.
        '''
        inj_factor = 1.0
        INJ_LO = 0.0
        try:
            dut = Dut(ScanBase.get_basil_dir(self)+'/examples/lab_devices/agilent33250a_pyserial.yaml')
            dut.init()
            logging.info('Connected to '+str(dut['Pulser'].get_info()))
        except RuntimeError:
            INJ_LO = 0.2
            inj_factor = 2.0
            logging.info('External injector not connected. Switch to internal one')
            self.dut['INJ_LO'].set_voltage(INJ_LO, unit='V')

        self.dut['global_conf']['PrmpVbpDac'] = 80
        self.dut['global_conf']['vthin1Dac'] = 255
        self.dut['global_conf']['vthin2Dac'] = 0
        self.dut['global_conf']['vffDac'] = 24
        self.dut['global_conf']['PrmpVbnFolDac'] = 51
        self.dut['global_conf']['vbnLccDac'] = 1
        self.dut['global_conf']['compVbnDac'] = 25
        self.dut['global_conf']['preCompVbnDac'] = 50

        self.dut.write_global()
        self.dut['control']['RESET'] = 0b01
        self.dut['control']['DISABLE_LD'] = 0
        self.dut['control']['PIX_D_CONF'] = 0
        self.dut['control'].write()

        self.dut['control']['CLK_OUT_GATE'] = 1
        self.dut['control']['CLK_BX_GATE'] = 1
        self.dut['control'].write()
        time.sleep(0.1)

        self.dut['control']['RESET'] = 0b11
        self.dut['control'].write()

        self.dut['global_conf']['OneSr'] = 1

        self.dut['global_conf']['TestHit'] = 0
        self.dut['global_conf']['SignLd'] = 0
        self.dut['global_conf']['InjEnLd'] = 0
        self.dut['global_conf']['TDacLd'] = 0
        self.dut['global_conf']['PixConfLd'] = 0
        self.dut.write_global()

        #self.dut['global_conf']['OneSr'] = 0  #all multi columns in parallel
        self.dut['global_conf']['ColEn'][:] = bitarray.bitarray([True] * 16) #(columns)
        self.dut['global_conf']['ColSrEn'][:] = bitarray.bitarray([True] * 16)
        self.dut.write_global()


        self.dut['pixel_conf'].setall(False)
        self.dut.write_pixel()
        self.dut['global_conf']['InjEnLd'] = 1
        self.dut.write_global()
        self.dut['global_conf']['InjEnLd'] = 0

        mask_en = np.full([64,64], False, dtype = np.bool)
        mask_tdac = np.full([64,64], 16, dtype = np.uint8)

        for inx, col in enumerate(columns):
           if col:
                mask_en[inx*4:(inx+1)*4,:]  = True

        if mask_filename:
            logging.info('Using pixel mask from file: %s', mask_filename)

            with tb.open_file(mask_filename, 'r') as in_file_h5:
                mask_tdac = in_file_h5.root.scan_results.tdac_mask[:]
                mask_en = in_file_h5.root.scan_results.en_mask[:]

        self.dut.write_en_mask(mask_en)
        self.dut.write_tune_mask(mask_tdac)

        self.dut['global_conf']['OneSr'] = 0
        self.dut.write_global()

        self.dut['inj'].set_delay(10000) #this seems to be working OK problem is probably bad injection on GPAC usually +0
        self.dut['inj'].set_width(1000)
        self.dut['inj'].set_repeat(repeat_command)
        self.dut['inj'].set_en(False)

        self.dut['trigger'].set_delay(400-4)
        self.dut['trigger'].set_width(16)
        self.dut['trigger'].set_repeat(1)
        self.dut['trigger'].set_en(True)

        ###
        self.dut['trigger'].set_delay(10000) #this seems to be working OK problem is probably bad injection on GPAC usually +0
        self.dut['trigger'].set_width(16)
        self.dut['trigger'].set_repeat(repeat_command)
#.........这里部分代码省略.........

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
# ------------------------------------------------------------
# Copyright (c) All rights reserved
# SiLab, Institute of Physics, University of Bonn
# ------------------------------------------------------------
#

import time
from basil.dut import Dut
import numpy as np


chip = Dut("sram_test.yaml")
chip.init()


def test_sram(count=10000):
    i = 0
    error = 0

    for k in range(count):

        # chip['CONTROL']['COUNTER_EN'] = 1
        # chip['CONTROL'].write()
        # chip['CONTROL']['COUNTER_EN'] = 0
        # chip['CONTROL'].write()

        chip['pulse'].set_delay(1)
        chip['pulse'].set_width((k + 1) % 3000)
        chip['pulse'].start()

        ret = chip['fifo'].get_data()

# 需要导入模块: from basil.dut import Dut [as 别名]
# 或者: from basil.dut.Dut import init [as 别名]
    def pre_run(self):
        # clear error queue in case run is executed a second time
        self.err_queue.queue.clear()
        # opening ZMQ context and binding socket
        if self._conf['send_data'] and not self._conf['zmq_context']:
            logging.info('Creating ZMQ context')
            self._conf['zmq_context'] = zmq.Context()  # contexts are thread safe unlike sockets
        else:
            logging.info('Using existing socket')
        # scan parameters
        if 'scan_parameters' in self._run_conf:
            if isinstance(self._run_conf['scan_parameters'], basestring):
                self._run_conf['scan_parameters'] = ast.literal_eval(self._run_conf['scan_parameters'])
            sp = namedtuple('scan_parameters', field_names=zip(*self._run_conf['scan_parameters'])[0])
            self.scan_parameters = sp(*zip(*self._run_conf['scan_parameters'])[1])
        else:
            sp = namedtuple_with_defaults('scan_parameters', field_names=[])
            self.scan_parameters = sp()
        logging.info('Scan parameter(s): %s', ', '.join(['%s=%s' % (key, value) for (key, value) in self.scan_parameters._asdict().items()]) if self.scan_parameters else 'None')

        # init DUT
        if not isinstance(self._conf['dut'], Dut):
            module_path = os.path.dirname(os.path.abspath(inspect.getfile(inspect.currentframe())))
            if isinstance(self._conf['dut'], basestring):
                # dirty fix for Windows pathes
                self._conf['dut'] = os.path.normpath(self._conf['dut'].replace('\\', '/'))
                # abs path
                if os.path.isabs(self._conf['dut']):
                    dut = self._conf['dut']
                # working dir
                elif os.path.exists(os.path.join(self._conf['working_dir'], self._conf['dut'])):
                    dut = os.path.join(self._conf['working_dir'], self._conf['dut'])
                # path of this file
                elif os.path.exists(os.path.join(module_path, self._conf['dut'])):
                    dut = os.path.join(module_path, self._conf['dut'])
                else:
                    raise ValueError('dut parameter not a valid path: %s' % self._conf['dut'])
            else:
                dut = self._conf['dut']
            dut = Dut(dut)

            # only initialize when DUT was not initialized before
            if 'dut_configuration' in self._conf and self._conf['dut_configuration']:
                if isinstance(self._conf['dut_configuration'], basestring):
                    # dirty fix for Windows pathes
                    self._conf['dut_configuration'] = os.path.normpath(self._conf['dut_configuration'].replace('\\', '/'))
                    # abs path
                    if os.path.isabs(self._conf['dut_configuration']):
                        dut_configuration = self._conf['dut_configuration']
                    # working dir
                    elif os.path.exists(os.path.join(self._conf['working_dir'], self._conf['dut_configuration'])):
                        dut_configuration = os.path.join(self._conf['working_dir'], self._conf['dut_configuration'])
                    # path of dut file
                    elif os.path.exists(os.path.join(os.path.dirname(dut.conf_path), self._conf['dut_configuration'])):
                        dut_configuration = os.path.join(os.path.dirname(dut.conf_path), self._conf['dut_configuration'])
                    # path of this file
                    elif os.path.exists(os.path.join(module_path, self._conf['dut_configuration'])):
                        dut_configuration = os.path.join(module_path, self._conf['dut_configuration'])
                    else:
                        raise ValueError('dut_configuration parameter not a valid path: %s' % self._conf['dut_configuration'])
                    # make dict
                    dut_configuration = RunManager.open_conf(dut_configuration)
                    # change bit file path
                    if 'USB' in dut_configuration and 'bit_file' in dut_configuration['USB'] and dut_configuration['USB']['bit_file']:
                        bit_file = os.path.normpath(dut_configuration['USB']['bit_file'].replace('\\', '/'))
                        # abs path
                        if os.path.isabs(bit_file):
                            pass
                        # working dir
                        elif os.path.exists(os.path.join(self._conf['working_dir'], bit_file)):
                            bit_file = os.path.join(self._conf['working_dir'], bit_file)
                        # path of dut file
                        elif os.path.exists(os.path.join(os.path.dirname(dut.conf_path), bit_file)):
                            bit_file = os.path.join(os.path.dirname(dut.conf_path), bit_file)
                        # path of this file
                        elif os.path.exists(os.path.join(module_path, bit_file)):
                            bit_file = os.path.join(module_path, bit_file)
                        else:
                            raise ValueError('bit_file parameter not a valid path: %s' % bit_file)
                        dut_configuration['USB']['bit_file'] = bit_file
                else:
                    dut_configuration = self._conf['dut_configuration']
            else:
                dut_configuration = None

            dut.init(dut_configuration)
            # assign dut after init in case of exceptions during init
            self._conf['dut'] = dut
            # additional init of the DUT
            self.init_dut()
        else:
            pass  # do nothing, already initialized
        # FIFO readout
        self.fifo_readout = FifoReadout(self.dut)
        # initialize the FE
        self.init_fe()