Python dut.Dut类代码示例

class TestSimGpio(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([os.getcwd() + '/test_SimGpio.v'])

        self.chip = Dut(cnfg_yaml)
        self.chip.init()

    def test_io(self):
        ret = self.chip['gpio'].get_data()
        self.assertEqual([0, 0, 0], ret)

        self.chip['gpio'].set_data([0xe3, 0xfa, 0x5a])
        ret = self.chip['gpio'].get_data()
        self.assertEqual([0, 0x5a, 0x5a], ret)

        self.chip['gpio'].set_output_en([0x0f, 0, 0])
        ret = self.chip['gpio'].get_data()
        self.assertEqual([0x33, 0x5a, 0x5a], ret)

    def test_io_register(self):
        self.chip['GPIO']['OUT'] = 0xa5
        self.chip['GPIO'].write()
        ret = self.chip['gpio'].get_data()
        self.assertEqual([0, 0xa5, 0xa5], ret)
        # TODO: Add register readback and comparison

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

class TestSimS2C(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([os.path.dirname(__file__) + '/test_SimI2c.v'])

        self.chip = Dut(cnfg_yaml)
        self.chip.init()

    def test_i2c(self):
        data = [0x85, 0x81, 0xa5, 0x91]
        self.chip['i2c'].write(0x92, data)

        ret = self.chip['i2c'].get_data(4)
        self.assertEqual(ret.tolist(), data)

        self.chip['i2c'].write(0x92, data[0:1])

        self.chip['i2c'].set_data([0, 1, 2, 3])

        ret = self.chip['i2c'].read(0x92, 3)
        self.assertEqual(ret.tolist(), data[1:])

        # no ack/no such device
        exept = False
        try:
            self.chip['i2c'].write(0x55, data)
        except IOError:
            exept = True

        self.assertEqual(exept, True)

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

class TestExampleMIO(unittest.TestCase):
    def setUp(self):

        fw_path = get_basil_dir() + "/firmware/modules"
        cocotb_compile_and_run(
            [
                fw_path + "/gpio/gpio.v",
                fw_path + "/utils/reset_gen.v",
                fw_path + "/utils/bus_to_ip.v",
                fw_path + "/utils/fx2_to_bus.v",
                os.path.dirname(__file__) + "/../src/example.v",
            ],
            top_level="example",
            sim_bus="basil.utils.sim.SiLibUsbBusDriver",
        )

        with open(os.path.dirname(__file__) + "/example.yaml", "r") as f:
            cnfg = yaml.load(f)

        # change to simulation interface
        cnfg["transfer_layer"][0]["type"] = "SiSim"

        self.chip = Dut(cnfg)
        self.chip.init()

    def test(self):

        ret = self.chip["GPIO_LED"].get_data()
        self.assertEqual([0], ret)

        self.chip["GPIO_LED"]["LED"] = 0x01
        self.chip["GPIO_LED"].write()

        ret = self.chip["GPIO_LED"].get_data()
        self.assertEqual([0x21], ret)

        self.chip["GPIO_LED"]["LED"] = 0x02
        self.chip["GPIO_LED"].write()

        ret = self.chip["GPIO_LED"].get_data()
        self.assertEqual([0x42], ret)

        self.chip["GPIO_LED"]["LED"] = 0x03
        self.chip["GPIO_LED"].write()

        ret = self.chip["GPIO_LED"].get_data()
        self.assertEqual([0x63], ret)

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

    def __init__(self, conf_file_name=None, voltage=1.5, conf_dict=None):
        """
        Initializes the chip, including turning on power.

        Exactly one of conf_file_name and conf_dict must be specified.

        This method also initializes the block lengths to their
        appropriate values.
        """
        if not (bool(conf_file_name) != bool(conf_dict)):
            raise ValueError("conf_file_name xor conf_dict must be specified.")
        elif conf_file_name:
            # Read in the configuration YAML file
            stream = open(conf_file_name, 'r')
            conf_dict = yaml.load(stream)
        else:  # conf_dict must be specified
            pass

        # Create the T3MAPSDriver object
        Dut.__init__(self, conf_dict)

        try:
            # Initialize the chip
            self.init()
        except NotImplementedError:  # this is to make simulation not fail
            print 'chip.init() :: NotImplementedError'

        # turn on the adapter card's power
        self['PWR']['EN_VD1'] = 1
        self['PWR']['EN_VD2'] = 1
        self['PWR']['EN_VA1'] = 1
        self['PWR']['EN_VA2'] = 1
        self['PWR'].write()

        # Set the output voltage on the pins
        self['PWRAC'].set_voltage("VDDD1", voltage)
        self['PWRAC'].set_voltage("VDDD2", voltage)

        # Set the "block lengths" for commands to pixel and global registers
        self._block_lengths['pixel'] = len(self['PIXEL_REG'])
        # 2 extra for load commands, 1 for the 'dropped' bit due to clock
        self._block_lengths['global'] = len(self['GLOBAL_REG']) + 2 +\
            self._global_dropped_bits
        # arbitrary length, but long enough to be detected by discriminator.
        self._block_lengths['inject'] = 500

        # Make sure the chip is reset
        self.reset_seq()

    def setUp(self):

        fw_path = get_basil_dir() + "/firmware/modules"
        cocotb_compile_and_run(
            [
                fw_path + "/gpio/gpio.v",
                fw_path + "/utils/reset_gen.v",
                fw_path + "/utils/bus_to_ip.v",
                fw_path + "/rrp_arbiter/rrp_arbiter.v",
                fw_path + "/utils/ODDR_sim.v",
                fw_path + "/utils/generic_fifo.v",
                fw_path + "/utils/cdc_pulse_sync.v",
                fw_path + "/utils/fx2_to_bus.v",
                fw_path + "/pulse_gen/pulse_gen.v",
                fw_path + "/pulse_gen/pulse_gen_core.v",
                fw_path + "/sram_fifo/sram_fifo_core.v",
                fw_path + "/sram_fifo/sram_fifo.v",
                os.path.dirname(__file__) + "/../firmware/src/sram_test.v",
                os.path.dirname(__file__) + "/../tests/tb.v",
            ],
            top_level="tb",
            sim_bus="basil.utils.sim.SiLibUsbBusDriver",
        )

        with open(os.path.dirname(__file__) + "/../sram_test.yaml", "r") as f:
            cnfg = yaml.load(f)

        # change to simulation interface
        cnfg["transfer_layer"][0]["type"] = "SiSim"

        self.chip = Dut(cnfg)
        self.chip.init()

    def setUp(self):

        fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
        cocotb_compile_and_run([
            os.path.join(fw_path, 'gpio/gpio.v'),
            os.path.join(fw_path, 'utils/reset_gen.v'),
            os.path.join(fw_path, 'utils/bus_to_ip.v'),
            os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'),
            os.path.join(fw_path, 'utils/ODDR_sim.v'),
            os.path.join(fw_path, 'utils/generic_fifo.v'),
            os.path.join(fw_path, 'utils/cdc_pulse_sync.v'),
            os.path.join(fw_path, 'utils/fx2_to_bus.v'),
            os.path.join(fw_path, 'pulse_gen/pulse_gen.v'),
            os.path.join(fw_path, 'pulse_gen/pulse_gen_core.v'),
            os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
            os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
            os.path.join(os.path.dirname(__file__), '../firmware/src/sram_test.v'),
            os.path.join(os.path.dirname(__file__), '../tests/tb.v')],
            top_level='tb',
            sim_bus='basil.utils.sim.SiLibUsbBusDriver'
        )

        with open(os.path.join(os.path.dirname(__file__), '../sram_test.yaml'), 'r') as f:
            cnfg = yaml.load(f)

        # change to simulation interface
        cnfg['transfer_layer'][0]['type'] = 'SiSim'

        self.chip = Dut(cnfg)
        self.chip.init()

class TestExampleMIO(unittest.TestCase):
    def setUp(self):
        fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
        cocotb_compile_and_run([
            os.path.join(fw_path, 'gpio/gpio.v'),
            os.path.join(fw_path, 'utils/reset_gen.v'),
            os.path.join(fw_path, 'utils/bus_to_ip.v'),
            os.path.join(fw_path, 'utils/fx2_to_bus.v'),
            os.path.join(os.path.dirname(__file__), '../src/example.v')],
            top_level='example',
            sim_bus='basil.utils.sim.SiLibUsbBusDriver'
        )

        with open(os.path.join(os.path.dirname(__file__), 'example.yaml'), 'r') as f:
            cnfg = yaml.load(f)

        # change to simulation interface
        cnfg['transfer_layer'][0]['type'] = 'SiSim'

        self.chip = Dut(cnfg)
        self.chip.init()

    def test_gpio(self):
        ret = self.chip['GPIO_LED'].get_data()
        self.assertEqual([0], ret)

        self.chip['GPIO_LED']['LED'] = 0x01
        self.chip['GPIO_LED'].write()

        ret = self.chip['GPIO_LED'].get_data()
        self.assertEqual([0x21], ret)

        self.chip['GPIO_LED']['LED'] = 0x02
        self.chip['GPIO_LED'].write()

        ret = self.chip['GPIO_LED'].get_data()
        self.assertEqual([0x42], ret)

        self.chip['GPIO_LED']['LED'] = 0x03
        self.chip['GPIO_LED'].write()

        ret = self.chip['GPIO_LED'].get_data()
        self.assertEqual([0x63], ret)

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

class Silab_relay(object):
    def __init__(self, yaml='relay.yaml'):
        self.dut = Dut(yaml)
        self.dut.init()
        time.sleep(1)
    
    def switch(self, channel, state='toggle'):
        '''
        Sets one channel of relay card to defined state or toggles
        '''
        if channel == 'All' or channel == 'all' or channel == 99:
            send_channel = 99
        elif type(channel) == int and channel >= 0 and channel <= 9:
            send_channel = channel + 2
        else:
            raise ValueError('Channel has to be integer between 0 and 9 or String \'All\'.')
            
        if state == 'On' or state == 'on' or state == 1 or state == True:
            send_state = 1
        elif state == 'Off' or state == 'off' or state == 0 or state == False:
            send_state = 0
        elif state == 'toggle' or state == 'Toggle':
            send_state = 0 if bool(self.get_state(channel)) else 1
            print send_state
            raise NotImplementedError
        else:
            raise ValueError('State has to be either 1/0 or \'On\'/\'Off\' or True/False.')
        
        self.dut['Arduino'].set_output(channel=send_channel, value=send_state)
    
    def switch_to(self, channel):
        self.switch('all', 'off')
        self.switch(channel, 'on')
        
    def get_state(self, channel='all'):
        '''
        Will only work as long as connection is open. On reconnect, the arduino resets and sets all pins to LOW.
        '''
        state = self.dut['Arduino'].get_state()

        if channel == 'all' or channel == 'All' or channel == 99:
            return state
        elif type(channel) == int and channel >= 0 and channel <= 9:
            return state[channel]
        else:
            raise ValueError('Channel has to be integer between 0 and 9 or String \'All\'.')

    def setUp(self):
        cocotb_compile_and_run([
            os.path.join(os.path.dirname(__file__), 'jtag_tap.v'),
            os.path.join(os.path.dirname(__file__), 'test_SimJtagGpio.v')]
        )

        self.chip = Dut(cnfg_yaml)
        self.chip.init(init_yaml)

class TestSimGpio(unittest.TestCase):
    def setUp(self):
        cocotb_compile_and_run([os.getcwd() + '/test_SimAdcRx.v'])

        self.chip = Dut(cnfg_yaml)
        self.chip.init()

    def test_io(self):
        pattern = [1, 0, 1, 1, 1, 2, 1, 3, 1, 4, 1, 5, 1, 6, 1, 7]
        self.chip['SEQ_GEN'].set_data(pattern)

        self.chip['PULSE_GEN'].set_delay(1)
        self.chip['PULSE_GEN'].set_width(1)

        self.chip['SEQ_GEN'].set_en_ext_start(True)
        self.chip['SEQ_GEN'].set_size(8)
        self.chip['SEQ_GEN'].set_repeat(1)

        # this is to have something in memory and not X
        self.chip['PULSE_GEN'].start()
        self.chip['SEQ_GEN'].is_done()
        self.chip['SEQ_GEN'].is_done()

        while(not self.chip['SEQ_GEN'].is_done()):
            pass

        # take some data
        self.chip['FADC'].set_align_to_sync(True)
        self.chip['FADC'].set_data_count(16)
        self.chip['FADC'].set_single_data(True)
        self.chip['FADC'].start()

        self.chip['PULSE_GEN'].start()
        self.chip['SEQ_GEN'].is_done()
        self.chip['SEQ_GEN'].is_done()

        while(not self.chip['FADC'].is_done()):
            pass

        ret = self.chip['fifo'].get_data()
        self.assertEqual(ret[2:2 + 8].tolist(), [0x0100, 0x0101, 0x0102, 0x0103, 0x0104, 0x0105, 0x0106, 0x0107])

    def tearDown(self):
        self.chip.close()  # let it close connection and stop simulator
        cocotb_compile_clean()

 def __init__(self,conf=""):
     self.init_log()
     if conf=="":
         conf="ccpdlf.yaml"
     self.dut=Dut(conf)
     self.debug=0
     self._build_img=np.vectorize(self._build_img_oneB)
     self.tdac=np.zeros([24,114],int)
     self.dut.init()
     self.set_DACcurrent()
     self.power()   

class TestSimScpi(unittest.TestCase):

    def setUp(self):
        cfg = yaml.load(cnfg_yaml)
        self.device = Dut(cfg)
        self.device.init()

    def test_read(self):
        self.assertEqual(self.device['Pulser'].get_frequency(), u'100.00')

    def test_write(self):
        self.device['Pulser'].set_on()
        self.assertEqual(self.device['Pulser'].get_on(), u'0')

    def test_exception(self):
        with self.assertRaises(ValueError):
            self.device['Pulser'].unknown_function()

    def tearDown(self):
        self.device.close()

    def test_default(self):
        self.cnfg['registers'][1]['fields'][0]['default'] = 0x01  # VINJECT
        self.dut = Dut(self.cnfg)
        self.dut.init()
        mem = dict()
#         mem[0] = 0  # reset
        mem[0] = 1
        mem[13] = 4
        mem[16] = 0x08
        mem[17] = 0
        mem[18] = 0
        self.dut['TEST2'].write()
        self.assertDictEqual(mem, self.dut['dummy_tl'].mem)

    def test_default(self):
        self.cnfg['registers'][1]['fields'][0]['default'] = 0x01  # VINJECT
        self.dut = Dut(self.cnfg)
        self.dut['spi_module']._require_version = "==1"
        self.dut.init()
        self.dut['spi_module']._mem_bytes = 32
        mem = dict()
#         mem[0] = 0  # reset
        mem[0] = 1
        mem[14] = 4
        mem[16] = 0x08
        mem[17] = 0
        mem[18] = 0
        self.dut['TEST2'].write()
        self.assertDictEqual(mem, self.dut['dummy_tl'].mem)

    def setUp(self):
        fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
        cocotb_compile_and_run([
            os.path.join(fw_path, 'gpio/gpio.v'),
            os.path.join(fw_path, 'utils/reset_gen.v'),
            os.path.join(fw_path, 'utils/bus_to_ip.v'),
            os.path.join(fw_path, 'utils/fx2_to_bus.v'),
            os.path.join(os.path.dirname(__file__), '../src/example.v')],
            top_level='example',
            sim_bus='basil.utils.sim.SiLibUsbBusDriver'
        )

        with open(os.path.join(os.path.dirname(__file__), 'example.yaml'), 'r') as f:
            cnfg = yaml.load(f)

        # change to simulation interface
        cnfg['transfer_layer'][0]['type'] = 'SiSim'

        self.chip = Dut(cnfg)
        self.chip.init()