本文整理汇总了C++中PacketPtr::getSize方法的典型用法代码示例。如果您正苦于以下问题：C++ PacketPtr::getSize方法的具体用法？C++ PacketPtr::getSize怎么用？C++ PacketPtr::getSize使用的例子？那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类PacketPtr的用法示例。
在下文中一共展示了PacketPtr::getSize方法的4个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: writeData
void PHXSimWrap::writeData(uint id, uint64_t addr, uint64_t clockcycle)
{
PRINTFN("%s: id=%d addr=%#lx clock=%lu\n",__func__,id,addr,clockcycle);
std::multimap< uint64_t, PacketPtr >::iterator it =
m_wr_pktMap.find( addr );
assert( it != m_wr_pktMap.end() );
PacketPtr pkt = it->second;
m_wr_lat.sample( curTick() - pkt->dram_enter_time );
PRINTFN("%s() `%s` addr=%#lx size=%d\n", __func__, pkt->cmdString().c_str(),
(long)pkt->getAddr(), pkt->getSize());
PhysicalMemory::doAtomicAccess( pkt );
if ( pkt->needsResponse() ) {
m_readyQ.push_back(pkt);
} else {
delete pkt;
}
m_wr_pktMap.erase( addr );
}示例2: if
void BridgeClassicToAMBATLM2<BUSWIDTH>::recvFunctional(PacketPtr pkt)
{
// std::cout << "Called recvFunctional" << std::endl;
tlm::tlm_generic_payload trans;
if (pkt->isRead())
trans.set_read();
else if (pkt->isWrite())
trans.set_write();
trans.set_address(pkt->getAddr());
trans.set_data_length(pkt->getSize());
// trans.set_streaming_width(TBD);
trans.set_data_ptr(pkt->getPtr<unsigned char>());
debug_port->transport_dbg(static_cast<tlm::tlm_generic_payload &>(trans));
}示例3: readData
void PHXSimWrap::readData(uint id, uint64_t addr, uint64_t clockcycle)
{
PRINTFN("%s: id=%d addr=%#lx clock=%lu\n",__func__,id,addr,clockcycle);
assert( m_rd_pktMap.find( addr ) != m_rd_pktMap.end() );
PacketPtr pkt = m_rd_pktMap[addr];
m_rd_lat.sample( curTick() - pkt->dram_enter_time );
PRINTFN("%s() `%s` addr=%#lx size=%d\n", __func__, pkt->cmdString().c_str(),
(long)pkt->getAddr(), pkt->getSize());
PhysicalMemory::doAtomicAccess( pkt );
m_readyQ.push_back(pkt);
m_rd_pktMap.erase( addr );
}示例4:
void BridgeClassicToAMBATLM2<BUSWIDTH>::sendWriteData()
{
PacketPtr pkt;
sc_core::sc_time delay= sc_core::SC_ZERO_TIME;
uint32_t width=(BUSWIDTH/8);
uint32_t burstLen=0;
uint32_t count=0;
uint32_t id = 0;
uint32_t dp_size = 0;
uint64_t address;
tlm::tlm_generic_payload* _trans;
tlm::tlm_phase ph;
amba::amba_id * m_id;
bool last=false;
while(true)
{
id = writeDataQueue.read();
pkt=wr_packets[id];
_trans=master_sock.get_transaction();
master_sock.reserve_data_size(*_trans, pkt->getSize()); //reserve the requested amount of data array bytes
_trans->set_command(tlm::TLM_WRITE_COMMAND);
address=pkt->getAddr();
burstLen = uint32_t(ceil(double_t(pkt->getSize()+address%width)/double_t(width)));
master_sock.template get_extension<amba::amba_id>(m_id,*_trans);
m_id->value=id;
master_sock.template validate_extension<amba::amba_id>(*_trans);
count=0;
memcpy(_trans->get_data_ptr(),pkt->getPtr<uint8_t>(),pkt->getSize());
dp_size=std::min(width-uint32_t(address%width),pkt->getSize());
uint32_t bytes_left=pkt->getSize();
// hanle the case where first dataphase is not aligned
if((address%width) != 0)
{
_trans->set_address(address);
_trans->set_data_length(dp_size);
if (burstLen == 1)
{
// std::cout << "TLM BEHAVIOR: TLM_WRITE_COMMAND & BEGIN_LAST_DATA 1 at time " << sc_core::sc_time_stamp() << "count= " << count << " burstLen=" << burstLen << std::endl;
ph= amba::BEGIN_LAST_DATA;
last=true;
}
else
{
// std::cout << "TLM BEHAVIOR: TLM_WRITE_COMMAND & BEGIN_DATA 1 at time " << sc_core::sc_time_stamp() << std::endl;
ph = amba::BEGIN_DATA;
last=false;
}
switch(master_sock->nb_transport_fw(*_trans,ph,delay))
{
case tlm::TLM_ACCEPTED:
// std::cout << "TLM BEHAVIOR: response=TLM_ACCEPTED at time " << sc_core::sc_time_stamp() << std::endl;
need_wenable_event=true;
wait(wenable_event);
break;
case tlm::TLM_UPDATED:
// std::cout << "TLM BEHAVIOR: response=TLM_UPDATED & END_DATA at time " << sc_core::sc_time_stamp() << std::endl;
assert(ph == amba::END_DATA);
break;
case tlm::TLM_COMPLETED:
// std::cout << "TLM BEHAVIOR: response=TLM_COMPLETED at time " << sc_core::sc_time_stamp() << std::endl;
abort();
break;
default:
abort();
break;
}
bytes_left -= dp_size;
count++;
address += dp_size;
//as per packet.cc:74 writeback never needs a response
if (last && (pkt->cmd != MemCmd::Writeback))
pkt->makeTimingResponse();
}
while(count<burstLen)
{
_trans->set_address(address);
if(count+1 >= burstLen)
{
// std::cout << "TLM BEHAVIOR: TLM_WRITE_COMMAND & BEGIN_LAST_DATA 2 at time " << sc_core::sc_time_stamp() << "count= " << count << " burstLen=" << burstLen << std::endl;
_trans->set_data_length(bytes_left);
ph= amba::BEGIN_LAST_DATA;
last=true;
}
else
{
// std::cout << "TLM BEHAVIOR: TLM_WRITE_COMMAND & BEGIN_DATA 2 at time " << sc_core::sc_time_stamp() << std::endl;
_trans->set_data_length(width);
last=false;
ph =amba::BEGIN_DATA;
}
// std::cout << sc_core::sc_object::name() <<" Sending the write transaction data, at time " << sc_core::sc_time_stamp() <<" BURST-COUNT="<< (count+1)<<std::endl;
switch(master_sock->nb_transport_fw(*_trans,ph,delay))
{
case tlm::TLM_ACCEPTED:
// std::cout << "TLM BEHAVIOR: received TLM_ACCEPTED at time " << sc_core::sc_time_stamp() << std::endl;
need_wenable_event=true;
wait(wenable_event);
/*count++;
address += width;
if (!last)
//.........这里部分代码省略.........