本文整理汇总了C++中Net::addpin方法的典型用法代码示例。如果您正苦于以下问题：C++ Net::addpin方法的具体用法？C++ Net::addpin怎么用？C++ Net::addpin使用的例子？那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类Net的用法示例。
在下文中一共展示了Net::addpin方法的1个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: parse
void XDLFile::parse(Design* cktdesign, NLFactory* cktfactory){
std::ifstream infile(getfilename().c_str());
assert(infile);
XDL_TAG tag;
string line;
Pin* curPin;
Port* curPort;
Cell* curCell;
Net* curNet;
Instance* curInstance;
NetTrace* curNettrace;
SliceConfig* curSliCfg;
Library* curLibrary = cktfactory->makeLibrary("primitive",cktdesign);
cktdesign->addlib(curLibrary);
XDLFactory* xdlfactory = new XDLFactory();
vector<string> ves;
// int line_index = 0;
stage = CKTSTAGEIGNORE;
while (getline(infile,line)){
// ++line_index;
// cout << "parsing line: " << line_index << endl;
if ( spaceline(line) || xdl_annotated_line(line) ) continue;
tag = getxdltag(line);
if (tag == XDLDESIGN){
parsexdldesign(ves,line);
xdldesign->setname(const_cast<char*>(ves.at(0).c_str()));
xdldesign->setdevice(const_cast<char*>(ves.at(1).c_str()));
xdldesign->setxdlversion(const_cast<char*>(ves.at(2).c_str()));
}
else if (tag == INST){
stage = CKTINST;
parsexdlinst(ves,line);
curCell = cktfactory->makeCell(ves.at(3).c_str(),ves.at(1).c_str(),curLibrary);
curInstance = cktfactory->makeInstance(ves.at(0).c_str(),NULL,curCell);
curSliCfg = xdlfactory->makeSlice(curInstance,ves.at(2).c_str());
curLibrary->addelem(curCell);
cktdesign->addinst(curInstance);
}
else if (tag == XDLNET){
stage = CKTNET;
parsexdlnet(ves,line);
curNet = cktfactory->makeNet(ves.at(0).c_str(),NULL);
NETTYPE type = ORDINARY;
if( !ves.at(1).compare("VCC") || !ves.at(1).compare("vcc") ) type = VCC;
if( !ves.at(1).compare("GND") || !ves.at(1).compare("gnd") ) type = GND;
curNettrace = xdlfactory->makeNet(curNet,type);
}
else if (tag == OUTPIN){
parsexdloutpin(ves,line);
Design::const_inst_iter iter;
XDLDesign::const_sliceIter sli_iter = xdldesign->findsite(ves.at(0).c_str());
bool b = cktdesign->findinst(iter,ves.at(0));
assert(b);
curPort = cktfactory->makePort(ves.at(1).c_str(),(*iter)->getcell());
curPin = cktfactory->makePin(ves.at(1).c_str(),*iter);
(*iter)->getcell()->addport(curPort);
(*iter)->addpin(curPin);
curNet->addpin(curPin);
curNet->addsrc(curPin);
curNettrace->setsrc(*sli_iter);
}
else if (tag == INPIN){
parsexdlinpin(ves,line);
Design::const_inst_iter iter;
XDLDesign::const_sliceIter sli_iter = xdldesign->findsite(ves.at(0).c_str());
bool b = cktdesign->findinst(iter,ves.at(0));
assert(b);
curPort = cktfactory->makePort(ves.at(1).c_str(),(*iter)->getcell());
curPin = cktfactory->makePin(ves.at(1).c_str(),*iter);
(*iter)->getcell()->addport(curPort);
(*iter)->addpin(curPin);
curNet->addpin(curPin);
curNet->addsink(curPin);
curNettrace->addsink(*sli_iter);
}
else{ //store the config info of the insts
if (!EndXdlElement(line)){
if(stage == CKTINST) curSliCfg->addConfigInfo(wipeoffword(line,string("cfg")));
}
}
if (EndXdlElement(line)){
if (stage == CKTINST) xdldesign->addslice(curSliCfg);
if (stage == CKTNET){
if(!curNettrace->getnet()->dangle()) xdldesign->addnet(curNettrace);
}
stage = CKTSTAGEIGNORE;
}
ves.clear();
}
infile.close();
}