Python TritonContext.processing方法代码示例

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
    def test_1(self):
        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.ONLY_ON_TAINTED, False)
        self.assertEqual(ctx.isModeEnabled(MODE.ONLY_ON_TAINTED), False)

        inst = Instruction("\x48\x89\xc3") # mov rbx, rax
        self.assertTrue(ctx.processing(inst))
        self.assertTrue(checkAstIntegrity(inst))

        self.assertEqual(len(inst.getReadRegisters()), 1)
        self.assertEqual(len(inst.getWrittenRegisters()), 2)

        ctx.enableMode(MODE.ONLY_ON_TAINTED, True)
        self.assertEqual(ctx.isModeEnabled(MODE.ONLY_ON_TAINTED), True)

        self.assertTrue(ctx.processing(inst))
        self.assertTrue(checkAstIntegrity(inst))

        self.assertEqual(len(inst.getSymbolicExpressions()), 0)
        self.assertEqual(len(inst.getReadRegisters()), 0)
        self.assertEqual(len(inst.getReadImmediates()), 0)
        self.assertEqual(len(inst.getWrittenRegisters()), 0)
        self.assertEqual(len(inst.getLoadAccess()), 0)
        self.assertEqual(len(inst.getStoreAccess()), 0)

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
class TestPathConstraint(unittest.TestCase):

    """Testing path constraint."""

    def setUp(self):
        """Define the arch."""
        self.ctx = TritonContext()
        self.ctx.setArchitecture(ARCH.X86)

        trace = [
            "\x25\xff\xff\xff\x3f",      # and eax, 0x3fffffff
            "\x81\xe3\xff\xff\xff\x3f",  # and ebx, 0x3fffffff
            "\x31\xd1",                  # xor ecx, edx
            "\x31\xfa",                  # xor edx, edi
            "\x31\xD8",                  # xor eax, ebx
            "\x0F\x84\x55\x00\x00\x00",  # je 0x55
        ]

        self.ctx.convertRegisterToSymbolicVariable(self.ctx.registers.eax)
        self.ctx.convertRegisterToSymbolicVariable(self.ctx.registers.ebx)

        for opcodes in trace:
            self.ctx.processing(Instruction(opcodes))

    def test_getPathConstraintsAst(self):
        """Test getPathConstraintsAst"""
        astCtx = self.ctx.getAstContext()
        crst = self.ctx.getPathConstraintsAst()
        self.assertNotEqual(len(self.ctx.getModel(crst)), 0)
        self.assertNotEqual(len(self.ctx.getModel(astCtx.lnot(crst))), 0)

    def test_getPathConstraints(self):
        """Test getPathConstraints"""
        pco = self.ctx.getPathConstraints()
        self.assertEqual(len(pco), 1)

    def test_isMultipleBranches(self):
        pc = self.ctx.getPathConstraints()[0]
        self.assertTrue(pc.isMultipleBranches())

    def test_getTakenPathConstraintAst(self):
        pc = self.ctx.getPathConstraints()[0]
        self.assertEqual(pc.getTakenPathConstraintAst().evaluate(), 1)

    def test_getTakenAddress(self):
        pc = self.ctx.getPathConstraints()[0]
        self.assertEqual(pc.getTakenAddress(), 91)

    def test_getBranchConstraints(self):
        pc = self.ctx.getPathConstraints()[0].getBranchConstraints()

        self.assertTrue(pc[0]['isTaken'])
        self.assertFalse(pc[1]['isTaken'])

        self.assertEqual(pc[0]['srcAddr'], pc[1]['srcAddr'])

        self.assertEqual(pc[0]['dstAddr'], 91)
        self.assertEqual(pc[1]['dstAddr'], 23)

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
    def test_known_issues(self):
        """Check tainting result after processing."""
        Triton = TritonContext()
        Triton.setArchitecture(ARCH.X86)

        Triton.taintRegister(Triton.registers.eax)
        inst = Instruction()
        # lea eax,[esi+eax*1]
        inst.setOpcode("\x8D\x04\x06")
        Triton.processing(inst)

        self.assertTrue(Triton.isRegisterTainted(Triton.registers.eax))
        self.assertFalse(Triton.isRegisterTainted(Triton.registers.ebx))

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
def test5():
    Triton = TritonContext()
    Triton.setArchitecture(ARCH.X86)
    astCtxt = Triton.getAstContext()

    # rax is now symbolic
    Triton.convertRegisterToSymbolicVariable(Triton.registers.eax)

    # process instruction
    Triton.processing(Instruction("\x83\xc0\x07")) # add eax, 0x7

    # get rax ast
    eaxAst = Triton.getAstFromId(Triton.getSymbolicRegisterId(Triton.registers.eax))

    # constraint
    c = eaxAst ^ 0x11223344 == 0xdeadbeaf

    print 'Test 5:', Triton.getModel(c)[0]

    return

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
    def test_3(self):
        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)

        inst = Instruction("\x48\x8b\x18") # mov rbx, qword ptr [rax]
        self.assertTrue(ctx.processing(inst))
        self.assertTrue(checkAstIntegrity(inst))

        self.assertEqual(len(inst.getReadRegisters()), 1)
        self.assertEqual(len(inst.getWrittenRegisters()), 2)
        self.assertEqual(len(inst.getLoadAccess()), 1)
        self.assertEqual(len(inst.getStoreAccess()), 0)

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
    def test_7(self):
        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.ONLY_ON_SYMBOLIZED, True)
        ctx.setConcreteRegisterValue(ctx.registers.rax, 0x1337)

        inst = Instruction("\x48\x8b\x18") # mov rbx, qword ptr [rax]
        self.assertTrue(ctx.processing(inst))
        self.assertTrue(checkAstIntegrity(inst))

        self.assertEqual(inst.getOperands()[1].getAddress(), 0x1337)
        self.assertIsNone(inst.getOperands()[1].getLeaAst())

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
    def test_2(self):
        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.ONLY_ON_TAINTED, True)
        ctx.taintRegister(ctx.registers.rax)

        inst = Instruction("\x48\x89\xc3") # mov rbx, rax
        self.assertTrue(ctx.processing(inst))
        self.assertTrue(checkAstIntegrity(inst))

        self.assertEqual(len(inst.getReadRegisters()), 1)
        self.assertEqual(len(inst.getWrittenRegisters()), 2)
        self.assertEqual(len(inst.getLoadAccess()), 0)
        self.assertEqual(len(inst.getStoreAccess()), 0)

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
    def test_4(self):
        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.ONLY_ON_SYMBOLIZED, True)
        ctx.convertRegisterToSymbolicVariable(ctx.registers.rax)

        inst = Instruction("\x48\x8b\x18") # mov rbx, qword ptr [rax]
        self.assertTrue(ctx.processing(inst))
        self.assertTrue(checkAstIntegrity(inst))

        self.assertEqual(len(inst.getReadRegisters()), 1)
        self.assertEqual(len(inst.getWrittenRegisters()), 0)
        self.assertEqual(len(inst.getLoadAccess()), 0)
        self.assertEqual(len(inst.getStoreAccess()), 0)

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
class TestLoadAccess(unittest.TestCase):

    """Testing the LOAD access semantics."""

    def test_load_immediate_fs(self):
        """Check load from fs segment with immediate."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86_64)

        inst = Instruction()
        # mov eax, DWORD PTR fs:0xffffffffffffdf98
        inst.setOpcode("\x64\x8B\x04\x25\x98\xDF\xFF\xFF")
        inst.setAddress(0x400000)

        self.Triton.setConcreteRegisterValue(self.Triton.registers.fs, 0x7fffda8ab700)
        self.Triton.processing(inst)

        self.assertTrue(inst.getLoadAccess())

        load, _ = inst.getLoadAccess()[0]
        self.assertEqual(load.getAddress(), 0x7fffda8a9698)
        self.assertEqual(load.getBitSize(), 32)

    def test_load_indirect_fs(self):
        """Check load from fs with indirect address."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86_64)

        inst = Instruction()
        # mov rax, QWORD PTR fs:[rax]
        inst.setOpcode("\x64\x48\x8B\x00")
        inst.setAddress(0x400000)

        self.Triton.setConcreteRegisterValue(self.Triton.registers.fs, 0x7fffda8ab700)
        self.Triton.setConcreteRegisterValue(self.Triton.registers.rax, 0xffffffffffffdf90)
        self.Triton.processing(inst)

        self.assertTrue(inst.getLoadAccess())

        load, _ = inst.getLoadAccess()[0]
        self.assertEqual(load.getAddress(), 0x7fffda8a9690)
        self.assertEqual(load.getBitSize(), 64)

    def test_load_ds(self):
        """Check load from ds segment."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86)

        inst = Instruction()
        # mov ax, ds:word_40213C
        inst.setOpcode("\x66\xA1\x3C\x21\x40\x00")
        self.Triton.processing(inst)

        self.assertEqual(inst.getOperands()[1].getAddress(), 0x40213C)
        self.assertEqual(inst.getOperands()[1].getBitSize(), 16)

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
class TestInstruction(unittest.TestCase):

    """Testing the Instruction class."""

    def setUp(self):
        """Define and process the instruction to test."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86_64)
        self.inst = Instruction()
        self.inst.setOpcode("\x48\x01\xd8")  # add rax, rbx
        self.inst.setAddress(0x400000)
        self.Triton.setConcreteRegisterValue(self.Triton.registers.rax, 0x1122334455667788)
        self.Triton.setConcreteRegisterValue(self.Triton.registers.rbx, 0x8877665544332211)
        self.Triton.processing(self.inst)

    def test_address(self):
        """Check instruction current and next address."""
        self.assertEqual(self.inst.getAddress(), 0x400000)
        self.assertEqual(self.inst.getNextAddress(), 0x400003)

    def test_memory(self):
        """Check memory access."""
        self.assertListEqual(self.inst.getLoadAccess(), [])
        self.assertListEqual(self.inst.getStoreAccess(), [])
        self.assertFalse(self.inst.isMemoryWrite())
        self.assertFalse(self.inst.isMemoryRead())

    def test_registers(self):
        """Check register access."""
        self.assertEqual(len(self.inst.getReadRegisters()), 2, "access RAX and RBX")
        self.assertEqual(len(self.inst.getWrittenRegisters()), 8, "write in RAX, RIP, AF, XF, OF, PF, SF and ZF")

    def test_taints(self):
        """Check taints attributes."""
        self.assertFalse(self.inst.isTainted())

    def test_prefix(self):
        """Check prefix data."""
        self.assertFalse(self.inst.isPrefixed())
        self.assertEqual(self.inst.getPrefix(), PREFIX.INVALID)

    def test_control_flow(self):
        """Check control flow flags."""
        self.assertFalse(self.inst.isControlFlow(), "It is not a jmp, ret or call")
        self.assertFalse(self.inst.isBranch(), "It is not a jmp")

    def test_condition(self):
        """Check condition flags."""
        self.assertFalse(self.inst.isConditionTaken())

    def test_opcode(self):
        """Check opcode informations."""
        self.assertEqual(self.inst.getOpcode(), "\x48\x01\xd8")
        self.assertEqual(self.inst.getType(), OPCODE.ADD)

    def test_thread(self):
        """Check threads information."""
        self.assertEqual(self.inst.getThreadId(), 0)

    def test_operand(self):
        """Check operand information."""
        self.assertEqual(len(self.inst.getOperands()), 2)
        self.assertEqual(self.inst.getOperands()[0].getName(), "rax")
        self.assertEqual(self.inst.getOperands()[1].getName(), "rbx")
        with self.assertRaises(Exception):
            self.inst.getOperands()[2]

    def test_symbolic(self):
        """Check symbolic information."""
        self.assertEqual(len(self.inst.getSymbolicExpressions()), 8)

    def test_size(self):
        """Check size information."""
        self.assertEqual(self.inst.getSize(), 3)

    def test_disassembly(self):
        """Check disassembly equivalent."""
        self.assertEqual(self.inst.getDisassembly(), "add rax, rbx")

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
class TestProcessing(unittest.TestCase):

    """Test processing for some error prone instruction."""

    def test_pop_esp(self):
        """Check pop on esp processing."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86)

        # mov esp, 0x19fe00
        inst1 = Instruction('\xBC\x00\xFE\x19\x00')
        # mov dword ptr [esp], 0x11111111
        inst2 = Instruction('\xC7\x04\x24\x11\x11\x11\x11')
        # pop dword ptr [esp]
        inst3 = Instruction('\x8F\x04\x24')
        self.Triton.processing(inst1)
        self.Triton.processing(inst2)
        self.Triton.processing(inst3)

        self.assertEqual(inst3.getOperands()[0].getAddress(), 0x19fe04, "esp has been poped")
        self.assertEqual(inst3.getStoreAccess()[0][0].getAddress(), 0x19fe04, "inst3 set the value in 0x19fe04")
        self.assertEqual(inst3.getStoreAccess()[0][1].evaluate(), 0x11111111, "And this value is 0x11111111")

    def test_pop(self):
        """Check the pop instruction processing."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86)

        # mov esp, 0x19fe00
        inst1 = Instruction('\xBC\x00\xFE\x19\x00')
        # mov edi, 0x19fe00
        inst2 = Instruction('\xBF\x00\xFE\x19\x00')
        # mov dword ptr [esp], 0x11111111
        inst3 = Instruction('\xC7\x04\x24\x11\x11\x11\x11')
        # pop dword ptr [edi]
        inst4 = Instruction('\x8F\x07')
        self.Triton.processing(inst1)
        self.Triton.processing(inst2)
        self.Triton.processing(inst3)
        self.Triton.processing(inst4)

        self.assertEqual(inst4.getOperands()[0].getAddress(), 0x19fe00, "poping edi doesn't change it")
        self.assertEqual(inst4.getStoreAccess()[0][0].getAddress(), 0x19fe00, "inst4 store the new value in 0x19fe00 (edi value)")
        self.assertEqual(inst4.getStoreAccess()[0][1].evaluate(), 0x11111111, "The stored value is 0x11111111")

    def test_mov_xmm_to_memory(self):
        """Check move and xmm register to memory do not crash."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86_64)

        # movhpd QWORD PTR [rax], xmm1
        self.Triton.processing(Instruction("\x66\x0F\x17\x08"))
        # movhpd xmm1, QWORD PTR [rax]
        self.Triton.processing(Instruction("\x66\x0F\x16\x08"))
        # movhps QWORD PTR [rax], xmm1
        self.Triton.processing(Instruction("\x0F\x17\x08"))
        # movhps xmm1, QWORD PTR [rax]
        self.Triton.processing(Instruction("\x0F\x16\x08"))
        # movlpd QWORD PTR [rax], xmm1
        self.Triton.processing(Instruction("\x66\x0F\x13\x08"))
        # movlpd xmm1, QWORD PTR [rax]
        self.Triton.processing(Instruction("\x66\x0F\x12\x08"))
        # movlps QWORD PTR [rax], xmm1
        self.Triton.processing(Instruction("\x0F\x13\x08"))
        # movlps xmm1, QWORD PTR [rax]
        self.Triton.processing(Instruction("\x0F\x12\x08"))

    def test_mix_high_low_register(self):
        """Check operation on lower and higher register."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86_64)
        inst = Instruction("\x00\xDC")  # add ah,bl
        self.Triton.processing(inst)

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
    #Set the arch
    Triton.setArchitecture(ARCH.X86_64)

    for (addr, opcode) in code:
        # Build an instruction
        inst = Instruction()

        # Setup opcode
        inst.setOpcode(opcode)

        # Setup Address
        inst.setAddress(addr)

        # Process everything
        Triton.processing(inst)

        # Display instruction
        print inst
        print '    ---------------'
        print '    Is memory read :', inst.isMemoryRead()
        print '    Is memory write:', inst.isMemoryWrite()
        print '    ---------------'
        for op in inst.getOperands():
            print '    Operand:', op
            if op.getType() == OPERAND.MEM:
                print '    - segment :', op.getSegmentRegister()
                print '    - base    :', op.getBaseRegister()
                print '    - index   :', op.getIndexRegister()
                print '    - scale   :', op.getScale()
                print '    - disp    :', op.getDisplacement()

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
    def test_taint_through_pointers(self):
        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.TAINT_THROUGH_POINTERS, False)

        ctx.taintRegister(ctx.registers.rax)
        self.assertTrue(ctx.isRegisterTainted(ctx.registers.rax))

        inst = Instruction("\x48\x0F\xB6\x18") # movzx  rbx,BYTE PTR [rax]
        inst.setAddress(0)
        ctx.processing(inst)

        self.assertFalse(ctx.isRegisterTainted(ctx.registers.rbx))

        ###########

        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.TAINT_THROUGH_POINTERS, True)

        ctx.taintRegister(ctx.registers.rax)
        self.assertTrue(ctx.isRegisterTainted(ctx.registers.rax))

        inst = Instruction("\x48\x0F\xB6\x18") # movzx  rbx,BYTE PTR [rax]
        inst.setAddress(0)
        ctx.processing(inst)

        self.assertTrue(ctx.isRegisterTainted(ctx.registers.rbx))

        ###########

        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.TAINT_THROUGH_POINTERS, True)

        ctx.taintRegister(ctx.registers.rax)
        self.assertTrue(ctx.isRegisterTainted(ctx.registers.rax))

        inst = Instruction("\x48\x89\x18") # mov [rax], rbx
        inst.setAddress(0x1000)
        ctx.processing(inst)

        self.assertFalse(ctx.isMemoryTainted(0))

        ###########

        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.TAINT_THROUGH_POINTERS, True)

        ctx.taintRegister(ctx.registers.rbx)
        self.assertTrue(ctx.isRegisterTainted(ctx.registers.rbx))

        inst = Instruction("\x48\x89\x18") # mov [rax], rbx
        inst.setAddress(0x1000)
        ctx.processing(inst)

        self.assertTrue(ctx.isMemoryTainted(0))

        ###########

        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.TAINT_THROUGH_POINTERS, True)

        ctx.taintRegister(ctx.registers.rax)
        self.assertTrue(ctx.isRegisterTainted(ctx.registers.rax))

        inst = Instruction("\x48\x31\x18") # xor [rax], rbx
        inst.setAddress(0x1000)
        ctx.processing(inst)

        self.assertFalse(ctx.isMemoryTainted(0))

        ###########

        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.TAINT_THROUGH_POINTERS, True)

        ctx.taintRegister(ctx.registers.rbx)
        self.assertTrue(ctx.isRegisterTainted(ctx.registers.rbx))

        inst = Instruction("\x48\x31\x18") # xor [rax], rbx
        inst.setAddress(0x1000)
        ctx.processing(inst)

        self.assertTrue(ctx.isMemoryTainted(0))

        ###########

        ctx = TritonContext()
        ctx.setArchitecture(ARCH.X86_64)
        ctx.enableMode(MODE.TAINT_THROUGH_POINTERS, True)

        ctx.taintMemory(0)
        inst = Instruction("\x48\x31\x18") # xor [rax], rbx
        inst.setAddress(0x1000)
        ctx.processing(inst)

#.........这里部分代码省略.........

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
class TestSymbolicExpression(unittest.TestCase):

    """Testing symbolic expression."""

    def setUp(self):
        """Define the arch."""
        self.ctx = TritonContext()
        self.ctx.setArchitecture(ARCH.X86_64)

        self.inst1 = Instruction("\x48\x31\xd8") # xor rax, rbx
        self.ctx.setConcreteRegisterValue(self.ctx.registers.al, 0x10)
        self.ctx.setConcreteRegisterValue(self.ctx.registers.bl, 0x55)

        self.inst2 = Instruction("\x48\x89\x03") # mov [rbx], rax

        self.ctx.processing(self.inst1)
        self.ctx.processing(self.inst2)

        self.expr1 = self.inst1.getSymbolicExpressions()[0]
        self.expr2 = self.inst2.getSymbolicExpressions()[8]

    def test_expressions(self):
        """Test expressions"""
        self.assertEqual(len(self.inst1.getSymbolicExpressions()), 7)

    def test_getAst(self):
        """Test getAst"""
        self.assertEqual(self.expr1.getAst().evaluate(), 0x45)

    def test_getComment(self):
        """Test getComment"""
        self.assertEqual(self.expr1.getComment(), "XOR operation")

    def test_getId(self):
        """Test getId"""
        self.assertEqual(self.expr1.getId(), 0)

    def test_getKind(self):
        """Test getKind"""
        self.assertEqual(self.expr1.getKind(), SYMEXPR.REG)
        self.assertEqual(self.expr2.getKind(), SYMEXPR.MEM)

    def test_getNewAst(self):
        """Test getNewAst"""
        self.assertTrue(self.expr1.getAst().equalTo(self.expr1.getNewAst()))

    def test_getOrigin(self):
        """Test getOrigin"""
        self.assertEqual(self.expr1.getOrigin().getId(), REG.X86_64.RAX)
        self.assertEqual(str(self.expr1.getOrigin()), "rax:64 bv[63..0]")
        self.assertEqual(str(self.expr2.getOrigin()), "[@0x55]:64 bv[63..0]")

    def test_isMemory(self):
        """Test isMemory"""
        self.assertFalse(self.expr1.isMemory())

    def test_isRegister(self):
        """Test isRegister"""
        self.assertTrue(self.expr1.isRegister())

    def test_isSymbolized(self):
        """Test isSymbolized"""
        self.assertFalse(self.expr1.isSymbolized())

    def test_isTainted(self):
        """Test isTainted"""
        self.assertFalse(self.expr1.isTainted())

    def test_setAst(self):
        """Test setAst"""
        self.expr1.setAst(self.ctx.getAstContext().bv(1, 64))
        self.assertEqual(str(self.expr1.getAst()), "(_ bv1 64)")

    def test_setComment(self):
        """Test setComment"""
        self.expr1.setComment("test")
        self.assertEqual(self.expr1.getComment(), "test")

# 需要导入模块: from triton import TritonContext [as 别名]
# 或者: from triton.TritonContext import processing [as 别名]
class TestSymbolic(unittest.TestCase):

    """Testing the symbolic engine."""

    def setUp(self):
        """Define the arch."""
        self.Triton = TritonContext()
        self.Triton.setArchitecture(ARCH.X86_64)
        self.astCtxt = self.Triton.getAstContext()

    def test_backup(self):
        """
        Check Symbolics value are saved when engine is disable.

        * Also check reseting a disable symbolic engines doesn't crash.
        """
        inst = Instruction()
        # update RAX
        inst.setOpcode("\x48\xFF\xC0")
        self.Triton.processing(inst)

        self.assertEqual(self.Triton.getSymbolicRegisterValue(self.Triton.registers.rax), 1)

        # This call triton::api.backupSymbolicEngine()
        self.Triton.enableSymbolicEngine(False)

        inst = Instruction()
        # update RAX again
        inst.setOpcode("\x48\xFF\xC0")
        self.Triton.processing(inst)

        self.assertEqual(self.Triton.getConcreteRegisterValue(self.Triton.registers.rax), 2, "concrete value is updated")
        self.assertEqual(self.Triton.getSymbolicRegisterValue(self.Triton.registers.rax), 1)
        self.assertEqual(self.Triton.getSymbolicRegisterValue(self.Triton.registers.rax), 1, "Symbolic value is not update")

        # Try to reset engine after a backup to test if the bug #385 is fixed.
        self.Triton.resetEngines()

    def test_bind_expr_to_memory(self):
        """Check symbolic expression binded to memory can be retrieve."""
        # Bind expr1 to 0x100
        expr1 = self.Triton.newSymbolicExpression(self.astCtxt.bv(0x11, 8))
        mem = MemoryAccess(0x100, CPUSIZE.BYTE)
        self.Triton.assignSymbolicExpressionToMemory(expr1, mem)

        # Get expr from memory
        expr2 = self.Triton.getSymbolicExpressionFromId(self.Triton.getSymbolicMemoryId(0x100))

        self.assertEqual(expr1.getAst().evaluate(), expr2.getAst().evaluate())

    def test_bind_expr_to_multi_memory(self):
        """Check symbolic expression binded to multiple memory location."""
        # Bind expr to multi memory location (0x100, 0x101, 0x102, 0x103)
        expr1 = self.Triton.newSymbolicExpression(self.astCtxt.bv(0x11223344, 32))
        mem = MemoryAccess(0x100, CPUSIZE.DWORD)
        self.Triton.assignSymbolicExpressionToMemory(expr1, mem)

        # Check we can get back the same values
        expr2 = self.Triton.getSymbolicExpressionFromId(self.Triton.getSymbolicMemoryId(0x100))
        expr3 = self.Triton.getSymbolicExpressionFromId(self.Triton.getSymbolicMemoryId(0x101))
        expr4 = self.Triton.getSymbolicExpressionFromId(self.Triton.getSymbolicMemoryId(0x102))
        expr5 = self.Triton.getSymbolicExpressionFromId(self.Triton.getSymbolicMemoryId(0x103))

        self.assertEqual(expr2.getAst().evaluate(), 0x44)
        self.assertEqual(expr3.getAst().evaluate(), 0x33)
        self.assertEqual(expr4.getAst().evaluate(), 0x22)
        self.assertEqual(expr5.getAst().evaluate(), 0x11)

        self.assertEqual(self.Triton.getSymbolicMemoryValue(mem), 0x11223344)

    def test_bind_expr_to_register(self):
        """Check symbolic expression binded to register."""
        expr1 = self.Triton.newSymbolicExpression(self.astCtxt.bv(0x11223344, 64))
        self.Triton.assignSymbolicExpressionToRegister(expr1, self.Triton.registers.rax)

        self.assertEqual(self.Triton.getSymbolicRegisterValue(self.Triton.registers.rax), 0x11223344)

        expr1 = self.Triton.newSymbolicExpression(self.astCtxt.bv(0x11223344, 32))
        with self.assertRaises(Exception):
            # Incorrect size
            self.Triton.assignSymbolicExpressionToRegister(expr1, self.Triton.registers.rax)