本文整理汇总了Python中migen.build.xilinx.XilinxPlatform.__init__方法的典型用法代码示例。如果您正苦于以下问题：Python XilinxPlatform.__init__方法的具体用法？Python XilinxPlatform.__init__怎么用？Python XilinxPlatform.__init__使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类migen.build.xilinx.XilinxPlatform的用法示例。
在下文中一共展示了XilinxPlatform.__init__方法的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io)
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.toolchain.ise_commands = """示例2: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self, hw_rev="v1.0"):
if hw_rev == "v1.0":
io_rev = _io_v1_0
elif hw_rev == "v1.1":
io_rev = _io_v1_1
else:
raise ValueError("Unknown hardware revision", hw_rev)
XilinxPlatform.__init__(
self, "xc7a100t-fgg484-2", _io_common + io_rev, _connectors,
toolchain="vivado")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
self.toolchain.bitstream_commands.extend([
# NOTE: disable this on Kasli/v1.0 boards where the XADC reference
# has not been fixed.
"set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]",
"set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]",
"set_property BITSTREAM.CONFIG.USERID \"{:#010x}\" [current_design]".format(self.userid),
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 2.5 [current_design]",
])示例3: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xc7a15t-csg325-1", _io, toolchain="vivado")
self.toolchain.bitstream_commands.extend([
# FIXME: enable this when the XADC reference wiring is fixed
# "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])示例4: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
if toolchain == "ise":
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
elif toolchain == "vivado":
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer示例5: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self, toolchain="vivado", programmer="vivado"):
XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")示例6: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xc3s500e-4pq208", _io)
self.toolchain.xst_opt = """-ifmt MIXED
-bram_utilization_ratio -1
-opt_level 2
-opt_mode SPEED
-register_balancing yes"""
self.toolchain.bitgen_opt += (" -g GTS_cycle:3 -g LCK_cycle:4 "
"-g GWE_cycle:5 -g DONE_cycle:6")
self.toolchain.ise_commands += """示例7: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self, larger=False):
chip = "xc7a50t-csg325-3" if larger else "xc7a35t-csg325-3"
XilinxPlatform.__init__(self, chip, _io,
toolchain="vivado", name="sayma_rtm")
self.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])示例8: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(
self, "xcku040-ffva1156-1-c", _io, _connectors,
toolchain="vivado")
self.toolchain.bitstream_commands.extend([
# FIXME: enable this when the XADC reference wiring is fixed
# "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])示例9: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx16-ftg256", _io, _connectors)示例10: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors,
toolchain="vivado")示例11: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io)示例12: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(
self, "xc7a100t-fgg484-2", _io, _connectors,
toolchain="vivado")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")示例13: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xc7a15t-csg325-1", _io, toolchain="vivado")示例14: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")示例15: __init__
# 需要导入模块: from migen.build.xilinx import XilinxPlatform [as 别名]
# 或者: from migen.build.xilinx.XilinxPlatform import __init__ [as 别名]
def __init__(self):
XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"