本文整理汇总了Python中migen.build.xilinx.XilinxPlatform类的典型用法代码示例。如果您正苦于以下问题：Python XilinxPlatform类的具体用法？Python XilinxPlatform怎么用？Python XilinxPlatform使用的例子？那么, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了XilinxPlatform类的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: __init__
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io)
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.toolchain.ise_commands = """示例2: __init__
def __init__(self, hw_rev="v1.0"):
if hw_rev == "v1.0":
io_rev = _io_v1_0
elif hw_rev == "v1.1":
io_rev = _io_v1_1
else:
raise ValueError("Unknown hardware revision", hw_rev)
XilinxPlatform.__init__(
self, "xc7a100t-fgg484-2", _io_common + io_rev, _connectors,
toolchain="vivado")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
self.toolchain.bitstream_commands.extend([
# NOTE: disable this on Kasli/v1.0 boards where the XADC reference
# has not been fixed.
"set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]",
"set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]",
"set_property BITSTREAM.CONFIG.USERID \"{:#010x}\" [current_design]".format(self.userid),
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 2.5 [current_design]",
])示例3: do_finalize
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("""
TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
""")
try:
ifclk = self.lookup_request("fx2_ifclk")
gpif = self.lookup_request("fx2_gpif")
for i, d in [(gpif.d, "in"), (gpif.d, "out"),
(gpif.ctl, "in"), (gpif.adr, "out"),
(gpif.slwr, "out"), (gpif.sloe, "out"),
(gpif.slrd, "out"), (gpif.pktend, "out")]:
if len(i) > 1:
q = "(*)"
else:
q = ""
self.add_platform_command("""
INST "{i}%s" TNM = gpif_net_%s;
""" % (q, d), i=i)
self.add_platform_command("""
NET "{ifclk}" TNM_NET = "GRPifclk";
TIMESPEC "TSifclk" = PERIOD "GRPifclk" 20833 ps HIGH 50%;
TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "{ifclk}" RISING;
TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "{ifclk}" RISING;
""", ifclk=ifclk)
except ConstraintError:
pass示例4: __init__
def __init__(self):
XilinxPlatform.__init__(self, "xc7a15t-csg325-1", _io, toolchain="vivado")
self.toolchain.bitstream_commands.extend([
# FIXME: enable this when the XADC reference wiring is fixed
# "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])示例5: __init__
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
if toolchain == "ise":
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
elif toolchain == "vivado":
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer示例6: __init__
def __init__(self, larger=False):
chip = "xc7a50t-csg325-3" if larger else "xc7a35t-csg325-3"
XilinxPlatform.__init__(self, chip, _io,
toolchain="vivado", name="sayma_rtm")
self.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])示例7: __init__
def __init__(self, toolchain="vivado", programmer="vivado"):
XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")示例8: __init__
def __init__(self):
XilinxPlatform.__init__(self, "xc3s500e-4pq208", _io)
self.toolchain.xst_opt = """-ifmt MIXED
-bram_utilization_ratio -1
-opt_level 2
-opt_mode SPEED
-register_balancing yes"""
self.toolchain.bitgen_opt += (" -g GTS_cycle:3 -g LCK_cycle:4 "
"-g GWE_cycle:5 -g DONE_cycle:6")
self.toolchain.ise_commands += """示例9: do_finalize
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(
self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
try:
self.add_period_constraint(
self.lookup_request("eth_clocks").tx, 8.0)
except ConstraintError:
pass示例10: __init__
def __init__(self):
XilinxPlatform.__init__(
self, "xcku040-ffva1156-1-c", _io, _connectors,
toolchain="vivado")
self.toolchain.bitstream_commands.extend([
# FIXME: enable this when the XADC reference wiring is fixed
# "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])示例11: do_finalize
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
eth_clocks = self.lookup_request("eth_clocks")
self.add_period_constraint(eth_clocks.rx, 40)
self.add_period_constraint(eth_clocks.tx, 40)
self.add_platform_command("""
TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
except ConstraintError:
pass示例12: do_finalize
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
if isinstance(self.toolchain, XilinxISEToolchain):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")示例13: do_finalize
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
clk_if = self.lookup_request("clk_if")
clk_fx = self.lookup_request("clk_fx")
self.add_platform_command("""
NET "{clk_if}" TNM_NET = "GRPclk_if";
NET "{clk_fx}" TNM_NET = "GRPclk_fx";
TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%;
TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%;
TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY;
TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY;
""", clk_if=clk_if, clk_fx=clk_fx)
except ConstraintError:
pass示例14: __init__
def __init__(self):
XilinxPlatform.__init__(
self, "xc7a100t-fgg484-2", _io, _connectors,
toolchain="vivado")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")示例15: __init__
def __init__(self):
XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io)