Python Ruby.create_system方法代码示例

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
if options.obj is None:
	print "Please specify the benchmark binary";
	sys.exit(1)
else:
	system.obj = options.obj
#Done addition by Tianyun

#Added by Tianyun for identifying debbie run from gem5 run
#if options.debbie is None:
#	print "Please sepcify debbie option"
#	sys.exit(1)
#else:
system.debbie = 0 #options.debbie
#Done addtion by Tianyun
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
Ruby.create_system(options, system, system.piobus, system._dma_ports)

for (i, cpu) in enumerate(system.cpu):
    #
    # Tie the cpu ports to the correct ruby system ports
    #
    cpu.createInterruptController()
    cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
    if buildEnv['TARGET_ISA'] == "x86":
        cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
        cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
        cpu.interrupts.pio = system.piobus.master
        cpu.interrupts.int_master = system.piobus.slave
        cpu.interrupts.int_slave = system.piobus.master

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
# system simulated
system = System(cpu = cpus,
                funcmem = SimpleMemory(in_addr_map = False),
                physmem = SimpleMemory(null = True),
                funcbus = NoncoherentBus(),
                clk_domain = SrcClockDomain(clock = options.sys_clock))

# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')

# All cpus are associated with cpu_clk_domain
for cpu in cpus:
    cpu.clk_domain = system.cpu_clk_domain

Ruby.create_system(options, system)

# Create a separate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)

assert(len(cpus) == len(system.ruby._cpu_ruby_ports))

for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
     #
     # Tie the cpu test and functional ports to the ruby cpu ports and
     # physmem, respectively
     #
     cpus[i].test = ruby_port.slave
     cpus[i].functional = system.funcbus.slave
     
     #

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
cpu = TimingSimpleCPU(cpu_id=0)
system = System(cpu = cpu, physmem = SimpleMemory(null = True))
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = '1GHz',
                                   voltage_domain = system.voltage_domain)

# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
                                       voltage_domain = system.voltage_domain)

system.mem_ranges = AddrRange('256MB')
system.piobus = NoncoherentBus()
Ruby.create_system(options, system, system.piobus)

# Create a separate clock for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                        voltage_domain = system.voltage_domain)

assert(len(system.ruby._cpu_ruby_ports) == 1)

# create the interrupt controller
cpu.createInterruptController()

#
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
def build_test_system(np):
    cmdline = cmd_line_template()
    if buildEnv['TARGET_ISA'] == "alpha":
        test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
                                        cmdline=cmdline)
    elif buildEnv['TARGET_ISA'] == "mips":
        test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
    elif buildEnv['TARGET_ISA'] == "sparc":
        test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
    elif buildEnv['TARGET_ISA'] == "x86":
        test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
                options.ruby, cmdline=cmdline)
    elif buildEnv['TARGET_ISA'] == "arm":
        test_sys = makeArmSystem(test_mem_mode, options.machine_type,
                                 options.num_cpus, bm[0], options.dtb_filename,
                                 bare_metal=options.bare_metal,
                                 cmdline=cmdline,
                                 external_memory=options.external_memory_system)
        if options.enable_context_switch_stats_dump:
            test_sys.enable_context_switch_stats_dump = True
    else:
        fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])

    # Set the cache line size for the entire system
    test_sys.cache_line_size = options.cacheline_size

    # Create a top-level voltage domain
    test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)

    # Create a source clock for the system and set the clock period
    test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
            voltage_domain = test_sys.voltage_domain)

    # Create a CPU voltage domain
    test_sys.cpu_voltage_domain = VoltageDomain()

    # Create a source clock for the CPUs and set the clock period
    test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
                                             voltage_domain =
                                             test_sys.cpu_voltage_domain)

    if options.kernel is not None:
        test_sys.kernel = binary(options.kernel)

    if options.script is not None:
        test_sys.readfile = options.script

    if options.lpae:
        test_sys.have_lpae = True

    if options.virtualisation:
        test_sys.have_virtualization = True

    test_sys.init_param = options.init_param

    # For now, assign all the CPUs to the same clock domain
    test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i,
                                 function_trace=options.enable_trace)
                    for i in xrange(np)]

    if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
        test_sys.vm = KvmVM()

    if options.ruby:
        # Check for timing mode because ruby does not support atomic accesses
        if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
            print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
            sys.exit(1)

        Ruby.create_system(options, True, test_sys, test_sys.iobus,
                           test_sys._dma_ports)

        # Create a seperate clock domain for Ruby
        test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                        voltage_domain = test_sys.voltage_domain)

        # Connect the ruby io port to the PIO bus,
        # assuming that there is just one such port.
        test_sys.iobus.master = test_sys.ruby._io_port.slave

        for (i, cpu) in enumerate(test_sys.cpu):
            #
            # Tie the cpu ports to the correct ruby system ports
            #
            cpu.clk_domain = test_sys.cpu_clk_domain
            cpu.createThreads()
            cpu.createInterruptController()

            cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
            cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave

            if buildEnv['TARGET_ISA'] == "x86":
                cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
                cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave

                cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
                cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
                cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master

    else:
#.........这里部分代码省略.........

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
check_flush = False
if buildEnv['PROTOCOL'] == 'MOESI_hammer':
    check_flush = True

tester = RubyTester(check_flush = check_flush,
                    checks_to_complete = options.checks,
                    wakeup_frequency = options.wakeup_freq)

#
# Create the M5 system.  Note that the PhysicalMemory Object isn't
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
system = System(tester = tester, physmem = PhysicalMemory())

system.ruby = Ruby.create_system(options, system)

assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))

#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True

for ruby_port in system.ruby._cpu_ruby_ports:
    #
    # Tie the ruby tester ports to the ruby cpu ports
    #
    tester.cpuPort = ruby_port.port

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
    if not options.fastmem:
        # Atomic CPU checked with fastmem option already
        fatal("SimPoint generation should be done with atomic cpu and fastmem")
    if np > 1:
        fatal("SimPoint generation not supported with more than one CPUs")

for i in xrange(np): 
    system.cpu[i].workload = process 
    print process.cmd

if options.ruby:
    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
        sys.exit(1)

    Ruby.create_system(options, False, system)
    assert(options.num_cpus == len(system.ruby._cpu_ports))

    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                        voltage_domain = system.voltage_domain)
    for i in xrange(np):
        ruby_port = system.ruby._cpu_ports[i]

        # Create the interrupt controller and connect its ports to Ruby
        # Note that the interrupt controller is always present but only
        # in x86 does it have message ports that need to be connected
        system.cpu[i].createInterruptController()

        # Connect the cpu's cache ports to Ruby
        system.cpu[i].icache_port = ruby_port.slave
        system.cpu[i].dcache_port = ruby_port.slave

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
                physmem = PhysicalMemory())

if options.num_dmas > 0:
    dmas = [ MemTest(atomic = False,
                     max_loads = options.maxloads,
                     issue_dmas = True,
                     percent_functional = 0,
                     percent_uncacheable = 0,
                     progress_interval = options.progress,
                     warn_on_failure = options.warn_on_failure) \
             for i in xrange(options.num_dmas) ]
    system.dma_devices = dmas
else:
    dmas = []

Ruby.create_system(options, system, dma_devices = dmas)

#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
 
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))

for (i, cpu) in enumerate(cpus):
    #
    # Tie the cpu memtester ports to the correct system ports
    #
    cpu.test = system.ruby._cpu_ruby_ports[i].port
    cpu.functional = system.funcmem.port

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
def build_test_system(np):
    if buildEnv['TARGET_ISA'] == "alpha":
        test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
    elif buildEnv['TARGET_ISA'] == "mips":
        test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
    elif buildEnv['TARGET_ISA'] == "sparc":
        test_sys = makeSparcSystem(test_mem_mode, bm[0])
    elif buildEnv['TARGET_ISA'] == "x86":
        test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
                options.ruby)
    elif buildEnv['TARGET_ISA'] == "arm":
        test_sys = makeArmSystem(test_mem_mode, options.machine_type,
                                 options.num_cpus, bm[0], options.dtb_filename,
                                 bare_metal=options.bare_metal)
        if options.enable_context_switch_stats_dump:
            test_sys.enable_context_switch_stats_dump = True
    else:
        fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])

    # Set the cache line size for the entire system
    test_sys.cache_line_size = options.cacheline_size

    # Create a top-level voltage domain
    test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)

    # Create a source clock for the system and set the clock period
    test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
            voltage_domain = test_sys.voltage_domain)

    # Create a CPU voltage domain
    test_sys.cpu_voltage_domain = VoltageDomain()

    # Create a source clock for the CPUs and set the clock period
    test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
                                             voltage_domain =
                                             test_sys.cpu_voltage_domain)

    if options.kernel is not None:
        test_sys.kernel = binary(options.kernel)

    if options.script is not None:
        test_sys.readfile = options.script

    if options.lpae:
        test_sys.have_lpae = True

    if options.virtualisation:
        test_sys.have_virtualization = True

    test_sys.init_param = options.init_param

    # For now, assign all the CPUs to the same clock domain
    test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
                    for i in xrange(np)]

    if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
        test_sys.vm = KvmVM()

    if options.ruby:
        # Check for timing mode because ruby does not support atomic accesses
        if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
            print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
            sys.exit(1)

        Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)

        # Create a seperate clock domain for Ruby
        test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                        voltage_domain = test_sys.voltage_domain)

        for (i, cpu) in enumerate(test_sys.cpu):
            #
            # Tie the cpu ports to the correct ruby system ports
            #
            cpu.clk_domain = test_sys.cpu_clk_domain
            cpu.createThreads()
            cpu.createInterruptController()

            cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
            cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave

            if buildEnv['TARGET_ISA'] == "x86":
                cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
                cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave

                cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
                cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
                cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master

            test_sys.ruby._cpu_ports[i].access_phys_mem = True

        # Create the appropriate memory controllers
        # and connect them to the IO bus
        test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
        for i in xrange(len(test_sys.mem_ctrls)):
            test_sys.mem_ctrls[i].port = test_sys.iobus.master

    else:
        if options.caches or options.l2cache:
            # By default the IOCache runs at the system clock
#.........这里部分代码省略.........

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
                     max_loads = options.maxloads,
                     issue_dmas = True,
                     percent_functional = 0,
                     percent_uncacheable = 0,
                     progress_interval = options.progress,
                     suppress_func_warnings =
                                        not options.suppress_func_warnings) \
             for i in xrange(options.num_dmas) ]
    system.dma_devices = dmas
else:
    dmas = []

dma_ports = []
for (i, dma) in enumerate(dmas):
    dma_ports.append(dma.test)
Ruby.create_system(options, False, system, dma_ports = dma_ports)

# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
                                   voltage_domain = system.voltage_domain)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                        voltage_domain = system.voltage_domain)

#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
class CPUClass(TimingSimpleCPU): pass
test_mem_mode = 'timing'
FutureClass = None

CPUClass.clock = options.clock

if buildEnv['TARGET_ISA'] == "alpha":
    system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
    system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
    setWorkCountOptions(system, options)
else:
    fatal("incapable of building non-alpha or non-x86 full system!")

system.ruby = Ruby.create_system(options,
                                 system,
                                 system.piobus,
                                 system._dma_devices)

system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]

for (i, cpu) in enumerate(system.cpu):
    #
    # Tie the cpu ports to the correct ruby system ports
    #
    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
    if buildEnv['TARGET_ISA'] == "x86":
        cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
        cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
        cpu.interrupts.pio = system.piobus.port
        cpu.interrupts.int_port = system.piobus.port

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
if options.kernel is not None:
    clusters[0].kernel = binary(options.kernel)

if options.script is not None:
    clusters[0].readfile = options.script

clusters[0].cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
clusters[1].cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
# Create a source clock for the CPUs and set the clock period
clusters[0].cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
                                       voltage_domain = clusters[0].voltage_domain)
clusters[1].cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
                                       voltage_domain = clusters[1].voltage_domain)

rubysystem0 = Ruby.create_system(options, clusters[0], clusters[0].piobus, clusters[0]._dma_ports)
rubysystem1 = Ruby.create_system(options, clusters[1], clusters[1].piobus, clusters[1]._dma_ports)

# Create a seperate clock domain for Ruby
clusters[0].ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                        voltage_domain = clusters[0].voltage_domain)
clusters[1].ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                        voltage_domain = clusters[1].voltage_domain)

for (i, cpu) in enumerate(clusters[0].cpu):
    #
    # Tie the cpu ports to the correct ruby system ports
    #
    cpu.clk_domain = clusters[0].cpu_clk_domain
    cpu.createThreads()
    cpu.createInterruptController()

# 需要导入模块: import Ruby [as 别名]
# 或者: from Ruby import create_system [as 别名]
                physmem = PhysicalMemory())

if options.num_dmas > 0:
    dmas = [ MemTest(atomic = False, \
                     max_loads = options.maxloads, \
                     issue_dmas = True, \
                     percent_functional = 0, \
                     percent_uncacheable = 0, \
                     progress_interval = options.progress) \
             for i in xrange(options.num_dmas) ]
    system.dma_devices = dmas
else:
    dmas = []

system.ruby = Ruby.create_system(options, \
                                 system, \
                                 dma_devices = dmas)

#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
 
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))

for (i, cpu) in enumerate(cpus):
    #
    # Tie the cpu memtester ports to the correct system ports
    #
    cpu.test = system.ruby._cpu_ruby_ports[i].port