Python Hardware.getDChains方法代码示例

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
	def QIE_mapping(self):
		# Records the uHTR slot, link, and channel of each QIE in master_dict
		failures=[]
		for j, qslot in enumerate(self.qcards):
			if self.V: print 'mapping qslot '+str(qslot)
			dc=hw.getDChains(qslot, self.bus)
			hw.SetQInjMode(0, qslot, self.bus)
			dc.read()
			
			for mapchip in [0,6]:
				try_map = True
				while try_map:

					for num in xrange(12):
						dc[num].PedestalDAC(-9)
						if num==mapchip:
							dc[num].PedestalDAC(31)
					dc.write()
					dc.read()
					info=self.get_mapping_histo()

					if info is not None:
						uhtr_slot=info[0]
						link=info[1]
						for i in xrange(6):
							if mapchip in range(6): self.add_QIE(qslot, i, uhtr_slot, link, 5-i)
							else: self.add_QIE(qslot, 6+i, uhtr_slot, link, 5-i)
						try_map = False

					elif mapchip == 5 or mapchip == 11:
						if j not in failures:
							print 'mapping qcard {0} failed really hard'.format(qslot)
							failures.append(j)
						try_map = False						

					else: mapchip += 1

			for chip in xrange(12):
				dc[chip].PedestalDAC(6)
				dc.write()
				dc.read()

		if len(failures) > 0:
			failures.reverse() 
			for failure in failures:
				a = self.qcards[failure]
				self.qcards.pop(failure)
				print "qcard {0} successfully popped from self.qcards".format(a)


		if self.V:
			for qslot in self.qcards:
				for chip in xrange(12):
					info=self.get_QIE_map(qslot, chip)
					print 'Q_slot: {4}, Qie: {3}, uhtr_slot: {0}, link: {1}, channel: {2}'.format(info[0], info[1], info[2], chip, qslot)

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
def setTimingThresholdDAC(slots, threshold_val, bus):

    for i_slot in slots: # all desired slots

        dcs = h.getDChains(i_slot,bus) # the 2 daisy chains from one QIE card
        dcs.read()

        for chip in xrange(12): # all 12 chips
            dcs[chip].TimingThresholdDAC(threshold_val) # change threshold

        dcs.write() # write the changes for both daisy chains

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
def setGsel(slots, gsel_val, bus):
    # valid gsel_val: 0,1,2,4,8,16,18,20,24
    # corresponds to 3.1, 4.65, 6.2, 9.3, 12.4, 15.5, 18.6, 21.7, 24.8 fC/LSB gain
    for i_slot in slots: # all desired slots

        dcs = h.getDChains(i_slot,bus) # the 2 daisy chains from one QIE card
        dcs.read()

        for chip in xrange(12): # all 12 chips
            dcs[chip].Gsel(gsel_val) # change gain

        dcs.write() # write the changes for both daisy chains

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
def setFixRangeModeOff(slots, bus):
    #fixed range mode = 1, autorange mode = 0

    for i_slot in slots: # all desired slots

        dcs = h.getDChains(i_slot, bus) # the 2 daisy chains from one QIE card
        dcs.read()

        for chip in xrange(12): # all 12 chips
            dcs[chip].FixRange(0) # turn fixed range OFF

        dcs.write() # write the changes for both daisy chains

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
def setPedestalDAC(slots, pedestal_val, bus):
    #pedestal = magnitude * 2 fC
    #takes magnitudes -31 to 31

    for i_slot in slots: # all desired slots

        dcs = h.getDChains(i_slot,bus) # the 2 daisy chains from one QIE card
        dcs.read()

        for chip in xrange(12): # all 12 chips
            dcs[chip].PedestalDAC(pedestal_val) # change pedestal

        dcs.write() # write the changes for both daisy chains

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
def setCapID0pedestal(slots, pedestal_val, bus):
    #pedestal = magnitude * ~1.9 fC
    #takes magnitudes -12 to 12

    for i_slot in slots: # all desired slots

        dcs = h.getDChains(i_slot,bus) # the 2 daisy chains from one QIE card
        dcs.read()

        for chip in xrange(12): # all 12 chips
            dcs[chip].CapID0pedestal(pedestal_val) # change pedestal

        dcs.write() # write the changes for both daisy chains

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
def printDaisyChain(slots, bus):
    for i_slot in slots: # all desired slots
        ''' makes instance of daisy chain class for each card '''
        dcs = h.getDChains(i_slot, bus) # the 2 daisy chains from one QIE card

        dcs.read() # get real values for 2 daisy chains

        print '\n\n>>>>>>>>>>>> SLOT %d <<<<<<<<<<<<<' %i_slot

        for chip in xrange(12):
            print '\n######## CHIP %d ########' %chip
            print dcs[chip]

        print '############################'

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
	def shunt_scan(self):
		peak_results = {}
		default_peaks = [] #holds the CI values for 3.1 fC/LSB setting for chips
		ratio_pf = [0,0] #pass/fail for ratio within 10% of nominal
		default_peaks_AVG = 0
		#GSel table gain values (in fC/LSB)
		# gain_settings = [3.1, 4.65, 6.2, 9.3, 12.4, 15.5, 18.6, 21.7, 24.8]
		# gain_settings = [0,1,2,4,8,16,18,20,24]
		gain_settings = [0]
		#ratio between default 3.1fC/LSB and itself/other GSel gains
		nominalGainRatios = [1.0, .67, .5, .33, .25, .2, .17, .14, 0.02]
		for setting in gain_settings:
			print "\n\n&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&"
			print "&&&&&&&&&&&&&&&&&&&& S E T. = %d &&&&&&&&&&&&&&&&&&&&&&&&" %setting
			print "&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&"

			for qslot in self.qcards:
				dc=hw.getDChains(qslot, self.bus)
				dc.read()
				hw.SetQInjMode(1, qslot, self.bus) #turn on CI mode (igloo function)
				i.displayCI(self.bus, qslot)
				for chip in xrange(12):
					dc[chip].PedestalDAC(31)
					dc[chip].ChargeInjectDAC(8640) #set max CI value
					dc[chip].Gsel(setting) #increase shunt/decrease gain
				dc.write()
				dc.read()

			histo_results=self.get_histo_results(self.crate, self.uhtr_slots, signalOn=True)

			for uhtr_slot, uhtr_slot_results in histo_results.iteritems():
				for chip, chip_results in uhtr_slot_results.iteritems():
					key="({0}, {1}, {2})".format(uhtr_slot, chip_results["link"], chip_results["channel"])
					if setting == 0: peak_results[key] = []
					peak_results[key].append(chip_results["signalBinMax"])
					if setting == 0 and chip_results['signalBinMax'] != 1:
						default_peaks.append(chip_results['signalBinMax'])

			print "\n\nPeak Results: ", peak_results,'\n\n\n\n\n'
			print "\n\n\n##########################################"
			print "##########################################\n"
			print "Default peaks: ", default_peaks

		total = 0
		for val in default_peaks:
			default_peaks_AVG += val
			total += 1
		default_peaks_AVG /= total

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
def setChargeInjectDAC(slots, charge_val, bus):
        # charge_val is decimal in fC:
        # 90   : (0,0,0),
        # 180  : (0,0,1),
        # 360  : (0,1,0),
        # 720  : (0,1,1),
        # 1440 : (1,0,0),
        # 2880 : (1,0,1),
        # 5760 : (1,1,0),
        # 8640 : (1,1,1)

    for i_slot in slots: # all desired slots

        dcs = h.getDChains(i_slot, bus) # the 2 daisy chains from one QIE card
        dcs.read()

        for chip in xrange(12): # all 12 chips
            dcs[chip].ChargeInjectDAC(charge_val)

        dcs.write() # write the changes for both daisy chains

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
	def charge_inject_test(self):
		ci_results = {} #ci=chargeinjection
		ci_settings = [90, 180, 360, 720, 1440, 2880, 5760, 8640] #in fC
		ci_results={}
		ci_results["settings"]=ci_settings
		for setting in ci_settings:
			for qslot in self.qcards:
				dc=hw.getDChains(qslot, self.bus)
				dc.read()
				for chip in xrange(12):
					dc[chip].ChargeInjectDAC(setting)
				dc.write()
				dc.read()
			histo_results=self.get_histo_results(self.crate, self.uhtr_slots)
			for uhtr_slot, uhtr_slot_results in histo_results.iteritems():
				for chip, chip_results in uhtr_slot_results.iteritems():
					key="({0}, {1}, {2})".format(uhtr_slot, chip_results["link"], chip_results["channel"])
					ci_results[key].append(chip_results["signalBinMax"])

		for qslot in self.qcards:
			for chip in xrange(12):
				ci_key=str(self.get_QIE_map(qslot, chip))
				chip_arr=ci_results[ci_key]

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
	def ped_test(self):
		ped_results = {}
		ped_settings = list(i-31 for i in xrange(63))
		ped_results={}
		ped_results["settings"]=ped_settings
		for setting in ped_settings:
			for qslot in self.qcards:
				dc=hw.getDChains(qslot, self.bus)
				dc.read()
				for chip in xrange(12):
					dc[chip].PedestalDAC(setting)
				dc.write()
				dc.read()
			histo_results=self.get_histo_results(self.crate, self.uhtr_slots)
			for uhtr_slot, uhtr_slot_results in histo_results.iteritems():
				for chip, chip_results in uhtr_slot_results.iteritems():
					key="({0}, {1}, {2})".format(uhtr_slot, chip_results["link"], chip_results["channel"])
					ped_results[key].append(chip_results["PedBinMax"])

		for qslot in self.qcards:
			for chip in xrange(12):
				ped_key=str(self.get_QIE_map(qslot, chip))
				chip_arr=ped_results[ped_key]

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
	def QIE_mapping(self):
		# Records the uHTR slot, link, and channel of each QIE in master_dict
		failures=[]
		for qslot in self.qcards:
			if self.V: print 'mapping qslot '+str(qslot)
			dc=hw.getDChains(qslot, self.bus)
			hw.SetQInjMode(0, qslot, self.bus)
			dc.read()
			for chip in [0,6]:
				for num in xrange(12):
					dc[num].PedestalDAC(-9)
					if num==chip:
						dc[num].PedestalDAC(31)
				dc.write()
				dc.read()
				info=self.get_mapping_histo()
				if info is not None:
					uhtr_slot=info[0]
					link=info[1]
					for i in xrange(6):
						self.add_QIE(qslot, chip+i, uhtr_slot, link, 5-i)
				else:
					print 'mapping qcard {0} failed'.format(qslot)
					failures.append(qslot)
			for chip in xrange(12):
				dc[chip].PedestalDAC(6)
				dc.write()
				dc.read()
		
#		for failure in failures:
#			self.qcards.remove(failure)

		if self.V:
			for qslot in self.qcards:
				for chip in xrange(12):
					info=self.get_QIE_map(qslot, chip)
					print 'Q_slot: {4}, Qie: {3}, uhtr_slot: {0}, link: {1}, channel: {2}'.format(info[0], info[1], info[2], chip, qslot)

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
	def QIE_mapping(self):
		# Records the uHTR slot, link, and channel of each QIE in master_dict
		for qslot in self.qcards:
			dc=hw.getDChains(qslot, self.bus)
			hw.SetQInjMode(0, qslot, self.bus)
			dc.read()
			for chip in [0,6]:
				for num in xrange(12):
					dc[num].PedestalDAC(-9)
					if num==chip:
						dc[num].PedestalDAC(31)
				dc.write()
				dc.read()
				info=self.get_mapping_histo()
				if info is not None:
					uhtr_slot=info[0]
					link=info[1]
					for i in xrange(6):
						self.add_QIE(qslot, chip+i, uhtr_slot, link, 5-i)
				else: print "mapping failed"
			for num in xrange(12):
				dc[num].PedestalDAC(-9)
				dc.write()
				dc.read()

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
	def ci_test(self, num_attempts=2):
		self.init_everything()

		attempts = range(num_attempts)
		histo_slopes = [] #stores all slopes for overall histogram
		adc = hw.ADCConverter()

		ci_settings = [90, 180, 360, 720, 1440, 2880, 5760, 8640] #in fC

		qslots = self.qcards
		for attempt in attempts:
			failures = []
			ci_results={}
			if self.V and  attempt > 0: print "\nRETEST attempt {1}, qcards: {0}\n".format(qslots, attempt)
			for setting in ci_settings:
				if self.V: print 'testing charge injection setting {0} fC'.format(setting)
				for qslot in qslots:
					hw.SetQInjMode(1, qslot, self.bus)
					dc=hw.getDChains(qslot, self.bus)
					dc.read()
					for chip in xrange(12):
						dc[chip].PedestalDAC(6)
						dc[chip].ChargeInjectDAC(setting)
						dc[chip].Gsel(0)
					dc.write()
					dc.read()
				histo_results=self.get_histo_results(self.crate, self.uhtr_slots, signalOn=True, out_dir="ci_histos_{0}".format(setting))

				for uhtr_slot, uhtr_slot_results in histo_results.iteritems():
					for chip, chip_results in uhtr_slot_results.iteritems():
						key="{0}_{1}_{2}".format(uhtr_slot, chip_results["link"], chip_results["channel"])
						if key not in ci_results: ci_results[key]=[]
						totalSignal = 0
						if 'signalBinMax_1' in chip_results:
							totalSignal = adc.linearize(chip_results['signalBinMax_1'])
							if 'signalBinMax_2' in chip_results:	# get 2nd peak if needed
								totalSignal += adc.linearize(chip_results['signalBinMax_2'])
							ci_results[key].append(totalSignal)

			#Turn off charge injection
			for qslot in qslots:
				hw.SetQInjMode(0, qslot, self.bus)

			#analyze results and make graphs
			cwd=os.getcwd()
			if not os.path.exists("ci_plots"):
				os.makedirs("ci_plots")
			os.chdir(cwd  + "/ci_plots")

			for qslot in qslots:

				cwd2=os.getcwd()
				if not os.path.exists(str(qslot)):
					os.makedirs(str(qslot))
				os.chdir(cwd2  + "/" + str(qslot))

				for chip in xrange(12):

					chip_map=self.get_QIE_map(qslot, chip)
					ci_key = "{0}_{1}_{2}".format(chip_map[0], chip_map[1], chip_map[2])
					chip_arr = ci_results[ci_key]

					slope = self.graph_results("ci", ci_settings, chip_arr, "{0}_{1}".format(qslot, chip))
					test_pass = False	
					if slope <= 1.15 and slope >=0.95: test_pass = True

					#update results
					if test_pass or attempt == attempts[-1]: 
						histo_slopes.append(slope)
						self.update_QIE_results(qslot, chip, "ci", test_pass)
					
					if not test_pass and qslot not in failures: failures.append(qslot)

					if attempt == 1: self.master_dict["ci_flags"] = failures					

					if self.V: print 'qslot: {0}, chip: {1}, slope: {2}, pass: {3}'.format(qslot, chip, slope, test_pass)

				os.chdir(cwd2)
			os.chdir(cwd)
			
			qslots = failures

		print "Failed cards: {0}".format(failures)		

		#make histogram of all slope results
		os.chdir(cwd + "/histo_statistics")	
		self.make_histo("ci", histo_slopes, 0.5, 1.5)
		os.chdir(cwd)

# 需要导入模块: import Hardware [as 别名]
# 或者: from Hardware import getDChains [as 别名]
from client import webBus
import Hardware as h
import iglooClass as i
# from TestSoftware.uHTR import uHTR

qcard_slots = [2,5]

b = webBus("pi5",0)
# uhtr = uHTR(6,qcard_slots,b)

#-------------------------------------
for slot in qcard_slots:
    print '__________________________________________________'
    print '____________________Slot %d_______________________' %slot
    print '__________________________________________________'
    myDC = h.getDChains(slot,b)

    # i.turnOnCI()
    d
    myDC.read()
    print myDC[0]

    print '__________________________________________________'
    print '__________________________________________________'
    print '__________________________________________________'

    # for num in xrange(12):
    #     for chip in xrange(12):
    #         myDC[chip].ChargeInjectDAC(8640)
    #         myDC[chip].PedestalDAC(-9)
    #         # myDC[chip].CapID0pedestal(0)