本文整理汇总了C++中tr::RealRegister::setAssignedRegister方法的典型用法代码示例。如果您正苦于以下问题:C++ RealRegister::setAssignedRegister方法的具体用法?C++ RealRegister::setAssignedRegister怎么用?C++ RealRegister::setAssignedRegister使用的例子?那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类tr::RealRegister
的用法示例。
在下文中一共展示了RealRegister::setAssignedRegister方法的4个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: cg
void TR::ARMSystemLinkage::initARMRealRegisterLinkage()
{
TR::Machine *machine = cg()->machine();
// make r15 (PC) unavailable for RA
TR::RealRegister *reg = machine->getRealRegister(TR::RealRegister::gr15);
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
// make r14 (LR) unavailable for RA
reg = machine->getRealRegister(TR::RealRegister::gr14);
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
// make r13 (SP) unavailable for RA
reg = machine->getRealRegister(TR::RealRegister::gr13);
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
// make r12 (IP) unavailable for RA
reg = machine->getRealRegister(TR::RealRegister::gr12);
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
// make r9 unavailable for RA (just in case, because it's meaning is platform defined)
reg = machine->getRealRegister(TR::RealRegister::gr9);
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
/*
* Note: we can assign the same weight to all registers because loads/stores
* can be done on multiple registers simultaneously.
*/
// assign "maximum" weight to registers r0-r8
for (int32_t r = TR::RealRegister::gr0; r <= TR::RealRegister::gr8; ++r)
{
machine->getRealRegister(static_cast<TR::RealRegister::RegNum>(r))->setWeight(0xf000);
}
// assign "maximum" weight to registers r10-r12
for (int32_t r = TR::RealRegister::gr10; r <= TR::RealRegister::gr12; ++r)
{
machine->getRealRegister(static_cast<TR::RealRegister::RegNum>(r))->setWeight(0xf000);
}
}
示例2: cg
void
TR::ARM64SystemLinkage::initARM64RealRegisterLinkage()
{
TR::Machine *machine = cg()->machine();
TR::RealRegister *reg;
int icount;
reg = machine->getARM64RealRegister(TR::RealRegister::RegNum::x16); // IP0
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
reg = machine->getARM64RealRegister(TR::RealRegister::RegNum::x17); // IP1
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
reg = machine->getARM64RealRegister(TR::RealRegister::RegNum::x29); // FP
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
reg = machine->getARM64RealRegister(TR::RealRegister::RegNum::x30); // LR
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
reg = machine->getARM64RealRegister(TR::RealRegister::RegNum::xzr); // zero or SP
reg->setState(TR::RealRegister::Locked);
reg->setAssignedRegister(reg);
// assign "maximum" weight to registers x0-x15
for (icount = TR::RealRegister::x0; icount <= TR::RealRegister::x15; icount++)
machine->getARM64RealRegister((TR::RealRegister::RegNum)icount)->setWeight(0xf000);
// assign "maximum" weight to registers x18-x28
for (icount = TR::RealRegister::x18; icount <= TR::RealRegister::x28; icount++)
machine->getARM64RealRegister((TR::RealRegister::RegNum)icount)->setWeight(0xf000);
// assign "maximum" weight to registers v0-v31
for (icount = TR::RealRegister::v0; icount <= TR::RealRegister::v31; icount++)
machine->getARM64RealRegister((TR::RealRegister::RegNum)icount)->setWeight(0xf000);
}
示例3: assignRegisters
void TR_PPCRegisterDependencyGroup::assignRegisters(TR::Instruction *currentInstruction,
TR_RegisterKinds kindToBeAssigned,
uint32_t numberOfRegisters,
TR::CodeGenerator *cg)
{
// *this swipeable for debugging purposes
TR::Machine *machine = cg->machine();
TR::Register *virtReg;
TR::RealRegister::RegNum dependentRegNum;
TR::RealRegister *dependentRealReg, *assignedRegister, *realReg;
int i, j;
TR::Compilation *comp = cg->comp();
int num_gprs = 0;
int num_fprs = 0;
int num_vrfs = 0;
// Use to do lookups using real register numbers
TR_PPCRegisterDependencyMap map(_dependencies, numberOfRegisters);
if (!comp->getOption(TR_DisableOOL))
{
for (i = 0; i< numberOfRegisters; i++)
{
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
if (dependentRegNum == TR::RealRegister::SpilledReg)
{
TR_ASSERT(virtReg->getBackingStorage(),"should have a backing store if dependentRegNum == spillRegIndex()\n");
if (virtReg->getAssignedRealRegister())
{
// this happens when the register was first spilled in main line path then was reverse spilled
// and assigned to a real register in OOL path. We protected the backing store when doing
// the reverse spill so we could re-spill to the same slot now
traceMsg (comp,"\nOOL: Found register spilled in main line and re-assigned inside OOL");
TR::Node *currentNode = currentInstruction->getNode();
TR::RealRegister *assignedReg = toRealRegister(virtReg->getAssignedRegister());
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(currentNode, (TR::SymbolReference*)virtReg->getBackingStorage()->getSymbolReference(), sizeof(uintptr_t), cg);
TR::InstOpCode::Mnemonic opCode;
TR_RegisterKinds rk = virtReg->getKind();
switch (rk)
{
case TR_GPR:
opCode =TR::InstOpCode::Op_load;
break;
case TR_FPR:
opCode = virtReg->isSinglePrecision() ? TR::InstOpCode::lfs : TR::InstOpCode::lfd;
break;
default:
TR_ASSERT(0, "\nRegister kind not supported in OOL spill\n");
break;
}
TR::Instruction *inst = generateTrg1MemInstruction(cg, opCode, currentNode, assignedReg, tempMR, currentInstruction);
assignedReg->setAssignedRegister(NULL);
virtReg->setAssignedRegister(NULL);
assignedReg->setState(TR::RealRegister::Free);
if (comp->getDebug())
cg->traceRegisterAssignment("Generate reload of virt %s due to spillRegIndex dep at inst %p\n",comp->getDebug()->getName(virtReg),currentInstruction);
cg->traceRAInstruction(inst);
}
if (!(std::find(cg->getSpilledRegisterList()->begin(), cg->getSpilledRegisterList()->end(), virtReg) != cg->getSpilledRegisterList()->end()))
cg->getSpilledRegisterList()->push_front(virtReg);
}
// we also need to free up all locked backing storage if we are exiting the OOL during backwards RA assignment
else if (currentInstruction->isLabel() && virtReg->getAssignedRealRegister())
{
TR::PPCLabelInstruction *labelInstr = (TR::PPCLabelInstruction *)currentInstruction;
TR_BackingStore * location = virtReg->getBackingStorage();
TR_RegisterKinds rk = virtReg->getKind();
int32_t dataSize;
if (labelInstr->getLabelSymbol()->isStartOfColdInstructionStream() && location)
{
traceMsg (comp,"\nOOL: Releasing backing storage (%p)\n", location);
if (rk == TR_GPR)
dataSize = TR::Compiler->om.sizeofReferenceAddress();
else
dataSize = 8;
location->setMaxSpillDepth(0);
cg->freeSpill(location,dataSize,0);
virtReg->setBackingStorage(NULL);
}
}
}
}
for (i = 0; i < numberOfRegisters; i++)
{
map.addDependency(_dependencies[i], i);
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
if (dependentRegNum != TR::RealRegister::SpilledReg)
{
if (virtReg->getKind() == TR_GPR)
num_gprs++;
else if (virtReg->getKind() == TR_FPR)
//.........这里部分代码省略.........
示例4: assignRegisters
void TR_ARMRegisterDependencyGroup::assignRegisters(TR::Instruction *currentInstruction,
TR_RegisterKinds kindToBeAssigned,
uint32_t numberOfRegisters,
TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Machine *machine = cg->machine();
TR::Register *virtReg;
TR::RealRegister::RegNum dependentRegNum;
TR::RealRegister *dependentRealReg, *assignedRegister;
uint32_t i, j;
bool changed;
if (!comp->getOption(TR_DisableOOL))
{
for (i = 0; i< numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
dependentRegNum = dependencies[i].getRealRegister();
if (dependentRegNum == TR::RealRegister::SpilledReg)
{
TR_ASSERT(virtReg->getBackingStorage(),"should have a backing store if dependentRegNum == spillRegIndex()\n");
if (virtReg->getAssignedRealRegister())
{
// this happens when the register was first spilled in main line path then was reverse spilled
// and assigned to a real register in OOL path. We protected the backing store when doing
// the reverse spill so we could re-spill to the same slot now
traceMsg (comp,"\nOOL: Found register spilled in main line and re-assigned inside OOL");
TR::Node *currentNode = currentInstruction->getNode();
TR::RealRegister *assignedReg = toRealRegister(virtReg->getAssignedRegister());
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(currentNode, (TR::SymbolReference*)virtReg->getBackingStorage()->getSymbolReference(), sizeof(uintptr_t), cg);
TR_ARMOpCodes opCode;
TR_RegisterKinds rk = virtReg->getKind();
switch (rk)
{
case TR_GPR:
opCode = ARMOp_ldr;
break;
case TR_FPR:
opCode = virtReg->isSinglePrecision() ? ARMOp_ldfs : ARMOp_ldfd;
break;
default:
TR_ASSERT(0, "\nRegister kind not supported in OOL spill\n");
break;
}
TR::Instruction *inst = generateTrg1MemInstruction(cg, opCode, currentNode, assignedReg, tempMR, currentInstruction);
assignedReg->setAssignedRegister(NULL);
virtReg->setAssignedRegister(NULL);
assignedReg->setState(TR::RealRegister::Free);
if (comp->getDebug())
cg->traceRegisterAssignment("Generate reload of virt %s due to spillRegIndex dep at inst %p\n", cg->comp()->getDebug()->getName(virtReg),currentInstruction);
cg->traceRAInstruction(inst);
}
if (!(std::find(cg->getSpilledRegisterList()->begin(), cg->getSpilledRegisterList()->end(), virtReg) != cg->getSpilledRegisterList()->end()))
cg->getSpilledRegisterList()->push_front(virtReg);
}
// we also need to free up all locked backing storage if we are exiting the OOL during backwards RA assignment
else if (currentInstruction->isLabel() && virtReg->getAssignedRealRegister())
{
TR::ARMLabelInstruction *labelInstr = (TR::ARMLabelInstruction *)currentInstruction;
TR_BackingStore *location = virtReg->getBackingStorage();
TR_RegisterKinds rk = virtReg->getKind();
int32_t dataSize;
if (labelInstr->getLabelSymbol()->isStartOfColdInstructionStream() && location)
{
traceMsg (comp,"\nOOL: Releasing backing storage (%p)\n", location);
if (rk == TR_GPR)
dataSize = TR::Compiler->om.sizeofReferenceAddress();
else
dataSize = 8;
location->setMaxSpillDepth(0);
cg->freeSpill(location,dataSize,0);
virtReg->setBackingStorage(NULL);
}
}
}
}
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
if (virtReg->getAssignedRealRegister()!=NULL)
{
if (dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
{
virtReg->block();
}
else
{
dependentRegNum = toRealRegister(virtReg->getAssignedRealRegister())->getRegisterNumber();
for (j=0; j<numberOfRegisters; j++)
{
if (dependentRegNum == dependencies[j].getRealRegister())
{
virtReg->block();
break;
}
//.........这里部分代码省略.........