C++ RealRegister::getRegisterNumber方法代码示例

uint32_t TR::AMD64FPConversionSnippet::getLength(int32_t estimatedSnippetStart)
   {
   // *this    swipeable for debugging purposes
   uint32_t length = 11;
   TR::Machine *machine = cg()->machine();


   if (toRealRegister(_convertInstruction->getTargetRegister())->getRegisterNumber() != TR::RealRegister::eax)
      {
      // MOV   R, rax
      // XCHG  R, rax
      //
      // 3 instruction/modRM bytes + 2 REX prefixes
      //
      length += (3 + 2);
      }

   TR::X86RegRegInstruction *instr = _convertInstruction->getIA32RegRegInstruction();
   TR_ASSERT(instr != NULL, "f2i conversion instruction must be either L4RegMem or CVTTSS2SIRegReg\n");
   TR::RealRegister *sourceRegister = toRealRegister(instr->getSourceRegister());
   if (sourceRegister->getRegisterNumber() != TR::RealRegister::xmm0)
      {
      length +=
           sizeof(pushBinary) + sizeof(popBinary)             // push and pop
         + 4 + (sourceRegister->rexBits(TR::RealRegister::REX_B, false)? 1 : 0) // MOVSD xmm0, source
         ;
      }

   return length + estimateRestartJumpLength(estimatedSnippetStart + length);
   }

static void assignFreeRegisters(TR::Instruction              *currentInstruction,
                                TR::RegisterDependency    *dep,
                                TR_PPCRegisterDependencyMap& map,
                                TR::CodeGenerator            *cg)
   {
   // *this    swipeable for debugging purposes
   TR::Machine *machine = cg->machine();

   // Assign a chain of dependencies where the head of the chain depends on a free reg
   while (dep)
      {
      TR_ASSERT(machine->getPPCRealRegister(dep->getRealRegister())->getState() == TR::RealRegister::Free, "Expecting free target register");
      TR::RealRegister *assignedReg = dep->getRegister()->getAssignedRealRegister() ?
         toRealRegister(dep->getRegister()->getAssignedRealRegister()) : NULL;
      machine->coerceRegisterAssignment(currentInstruction, dep->getRegister(), dep->getRealRegister());
      dep->getRegister()->block();
      dep = assignedReg ?
         map.getDependencyWithTarget(assignedReg->getRegisterNumber()) : NULL;
      }
   }

static void assignContendedRegisters(TR::Instruction              *currentInstruction,
                                     TR::RegisterDependency    *dep,
                                     TR_PPCRegisterDependencyMap& map,
                                     bool                         depsBlocked,
                                     TR::CodeGenerator            *cg)
   {
   // *this    swipeable for debugging purposes
   TR::Machine *machine = cg->machine();

   dep = findDependencyChainHead(dep, map);


   TR::Register *virtReg = dep->getRegister();
   TR::RealRegister::RegNum targetRegNum = dep->getRealRegister();
   TR::RealRegister *targetReg = machine->getPPCRealRegister(targetRegNum);
   TR::RealRegister *assignedReg = virtReg->getAssignedRealRegister() ?
      toRealRegister(virtReg->getAssignedRealRegister()) :  NULL;


   // Chain of length 1
   if (!assignedReg || !map.getDependencyWithTarget(assignedReg->getRegisterNumber()))
      {
      machine->coerceRegisterAssignment(currentInstruction, virtReg, targetRegNum);
      virtReg->block();
      return;
      }
   // Chain of length 2, handled here instead of below to get 3*xor exchange on GPRs
   if (map.getDependencyWithTarget(assignedReg->getRegisterNumber()) == map.getDependencyWithAssigned(targetRegNum))
      {
      TR::Register *targetVirtReg = targetReg->getAssignedRegister();
      machine->coerceRegisterAssignment(currentInstruction, virtReg, targetRegNum);
      virtReg->block();
      targetVirtReg->block();
      return;
      }

   // Grab a spare reg in order to free the target of the first dep
   // At this point the first dep's target could be blocked, assigned, or NoReg
   // If it's blocked or assigned we allocate a spare and assign the target's virtual to it
   // If it's NoReg, the spare reg will be used as the first dep's actual target
   TR::RealRegister *spareReg = machine->findBestFreeRegister(currentInstruction, virtReg->getKind(),
                                                                targetRegNum == TR::RealRegister::NoReg ? dep->getExcludeGPR0() : false, false,
                                                                targetRegNum == TR::RealRegister::NoReg ? virtReg : targetReg->getAssignedRegister());
   bool                haveFreeSpare = spareReg != NULL;
   if (!spareReg)
      {
      // If the regs in this dep group are not blocked we need to make sure we don't spill a reg that's in the middle of the chain
      if (!depsBlocked)
         {
         if (targetRegNum == TR::RealRegister::NoReg)
            spareReg = machine->freeBestRegister(currentInstruction,
                                                 map.getDependencyWithTarget(assignedReg->getRegisterNumber())->getRegister(),
                                                 assignedReg, false);
         else
            spareReg = machine->freeBestRegister(currentInstruction, virtReg, targetReg, false);
         }
      else
         {
         if (targetRegNum == TR::RealRegister::NoReg)
            spareReg = machine->freeBestRegister(currentInstruction, virtReg, NULL, dep->getExcludeGPR0());
         else
            spareReg = machine->freeBestRegister(currentInstruction, targetReg->getAssignedRegister(), NULL, false);
         }
      }

   if (targetRegNum != TR::RealRegister::NoReg && spareReg != targetReg)
      {
      machine->coerceRegisterAssignment(currentInstruction, targetReg->getAssignedRegister(), spareReg->getRegisterNumber());
      }

   TR_ASSERT(targetRegNum == TR::RealRegister::NoReg ||
          targetReg->getState() == TR::RealRegister::Free, "Expecting free target register");

   if (depsBlocked || targetRegNum != TR::RealRegister::NoReg || haveFreeSpare)
      {

      machine->coerceRegisterAssignment(currentInstruction, virtReg,
                                        targetRegNum == TR::RealRegister::NoReg ?
                                        spareReg->getRegisterNumber() : targetRegNum);
      virtReg->block();
      }

   dep = map.getDependencyWithTarget(assignedReg->getRegisterNumber());
   while (dep)
      {
      virtReg = dep->getRegister();
      targetRegNum = dep->getRealRegister();
      targetReg = machine->getPPCRealRegister(targetRegNum);
      assignedReg = virtReg->getAssignedRealRegister() ?
         toRealRegister(virtReg->getAssignedRealRegister()) : NULL;

      TR_ASSERT(targetReg->getState() == TR::RealRegister::Free || targetReg == spareReg,
             "Expecting free target register or target to have been filled to free spare register");

      machine->coerceRegisterAssignment(currentInstruction, virtReg, targetRegNum);
      virtReg->block();
      dep = assignedReg ?
         map.getDependencyWithTarget(assignedReg->getRegisterNumber()) : NULL;
      }

//.........这里部分代码省略.........

uint8_t *TR::X86FPConvertToIntSnippet::genFPConversion(uint8_t *buffer)
   {
   TR::ILOpCodes              opcode          = _convertInstruction->getNode()->getOpCodeValue();
   TR::RealRegister          *targetRegister  = toRealRegister(_convertInstruction->getTargetRegister());
   TR::RealRegister::RegNum   targetReg       = targetRegister->getRegisterNumber();

   TR::Machine *machine = cg()->machine();

   TR_ASSERT(cg()->getProperties().getIntegerReturnRegister() == TR::RealRegister::eax, "Only support integer return in eax");

   if (targetReg != TR::RealRegister::eax)
      {
      // MOV R, eax
      //
      *buffer++ = 0x8b;
      *buffer = 0xc0;
      targetRegister->setRegisterFieldInModRM(buffer);
      buffer++;
      }

   // Push the floating-point value on to the stack before calling the helper.
   //
   // SUB esp, 4/8
   //
   *buffer++ = 0x83;
   *buffer++ = 0xec;
   if (opcode == TR::f2i)
      *buffer++ = 0x04;
   else
      *buffer++ = 0x08;

   if (_convertInstruction->getIA32RegMemInstruction())
      {
      // FST [esp], st0
      //
      if (opcode == TR::f2i)
         *buffer++ = 0xd9;
      else
         *buffer++ = 0xdd;
      *buffer++ = 0x14;
      *buffer++ = 0x24;
      }
   else
      {
      TR::X86RegRegInstruction  *instr = _convertInstruction->getIA32RegRegInstruction();
      TR_ASSERT(instr != NULL, "f2i conversion instruction must be either L4RegMem or CVTTSS2SIRegReg\n");

      TR::RealRegister *sourceRegister = toRealRegister(instr->getSourceRegister());

      // MOVSS/MOVSD [esp], source
      //
      if (opcode == TR::f2i)
         *buffer++ = 0xf3;
      else
         *buffer++ = 0xf2;
      *buffer++ = 0x0f;
      *buffer++ = 0x11;
      *buffer = 0x04;
      sourceRegister->setRegisterFieldInModRM(buffer);
      buffer++;
      *buffer++ = 0x24;
      }

   // Call the helper
   //
   buffer = emitCallToConversionHelper(buffer);

   // ADD esp, 4/8
   //
   *buffer++ = 0x83;
   *buffer++ = 0xc4;
   if (opcode == TR::f2i)
      *buffer++ = 0x04;
   else
      *buffer++ = 0x08;

   if (targetReg != TR::RealRegister::eax)
      {
      // XCHG R, eax
      //
      *buffer = 0x90;
      targetRegister->setRegisterFieldInOpcode(buffer);
      buffer++;
      }

   return buffer;
   }

void
TR_Debug::print(TR::FILE *pOutFile, TR::X86FPConvertToIntSnippet  * snippet)
   {
   if (pOutFile == NULL)
      return;

   uint8_t *bufferPos = snippet->getSnippetLabel()->getCodeLocation();

   printSnippetLabel(pOutFile, snippet->getSnippetLabel(), bufferPos, getName(snippet));

   TR::RealRegister *targetRegister = toRealRegister(snippet->getConvertInstruction()->getTargetRegister());
   uint8_t              reg = targetRegister->getRegisterNumber();

   if (reg != TR::RealRegister::eax)
      {
      printPrefix(pOutFile, NULL, bufferPos, 2);
      trfprintf(pOutFile, "mov\t");
      print(pOutFile, targetRegister, TR_WordReg);
      trfprintf(pOutFile, ", eax\t\t%s preserve helper return reg",
                    commentString());
      bufferPos += 2;
      }

   printPrefix(pOutFile, NULL, bufferPos, 3);
   trfprintf(pOutFile, "sub\tesp, 4\t\t%s push parameter",
                 commentString());
   bufferPos += 3;

   TR::X86RegRegInstruction  *instr = snippet->getConvertInstruction()->getIA32RegRegInstruction();

   if (instr)
      {
      printPrefix(pOutFile, NULL, bufferPos, 5);
      trfprintf(pOutFile, "movss\t dword ptr [esp], ");
      print(pOutFile, toRealRegister(instr->getSourceRegister()), TR_QuadWordReg);
      bufferPos += 5;
      }
   else
      {
      printPrefix(pOutFile, NULL, bufferPos, 3);
      trfprintf(pOutFile, "fst\tdword ptr [esp]");
      bufferPos += 3;
      }

   printPrefix(pOutFile, NULL, bufferPos, 5);
   trfprintf(pOutFile, "call\t%s", getName(snippet->getHelperSymRef()));
   bufferPos += 5;

   printPrefix(pOutFile, NULL, bufferPos, 3);
   trfprintf(pOutFile, "add\tesp, 4\t\t%s pop parameter",
                 commentString());
   bufferPos += 3;

   if (reg != TR::RealRegister::eax)
      {
      printPrefix(pOutFile, NULL, bufferPos, 1);
      trfprintf(pOutFile, "xchg\teax, ");
      print(pOutFile, targetRegister, TR_WordReg);
      trfprintf(pOutFile, "\t\t%s restore eax",
                    commentString());
      bufferPos++;
      }

   printRestartJump(pOutFile, snippet, bufferPos);
   }

uint8_t *TR::AMD64FPConversionSnippet::genFPConversion(uint8_t *buffer)
   {
   // *this    swipeable for debugging purposes

   // This didn't end up as clean as I thought.  TODO:AMD64: Separate out the 64-bit code into another class.

   TR::ILOpCodes              opCode          = _convertInstruction->getNode()->getOpCodeValue();
   TR::RealRegister          *targetRegister  = toRealRegister(_convertInstruction->getTargetRegister());
   TR::RealRegister::RegNum   targetReg       = targetRegister->getRegisterNumber();
   TR::Machine               *machine         = cg()->machine();
   const TR::X86LinkageProperties &properties = cg()->getProperties();

   uint8_t *originalBuffer = buffer;

   TR_ASSERT(properties.getIntegerReturnRegister() == TR::RealRegister::eax, "Only support integer return in eax");

   if (targetReg != TR::RealRegister::eax)
      {
      // MOV R, rax
      //
      *buffer++ = TR::RealRegister::REX | TR::RealRegister::REX_W | targetRegister->rexBits(TR::RealRegister::REX_R, false);
      *buffer++ = 0x8b;
      *buffer = 0xc0;
      targetRegister->setRegisterFieldInModRM(buffer);
      buffer++;
      }

   TR_ASSERT(properties.getFloatArgumentRegister(0) == TR::RealRegister::xmm0, "Only support 1st FP arg in xmm0");
   TR::X86RegRegInstruction *instr = _convertInstruction->getIA32RegRegInstruction();
   TR_ASSERT(instr != NULL, "conversion instruction must be CVTTSS2SIRegReg\n");

   TR::RealRegister         *sourceRegister = toRealRegister(instr->getSourceRegister());
   TR::RealRegister::RegNum  sourceReg      = sourceRegister->getRegisterNumber();

   // Save xmm0 if necessary
   //
   if (sourceReg != TR::RealRegister::xmm0)
      {
      TR_ASSERT(TR::Compiler->target.is64Bit(), "This push sequence only works on AMD64");
      memcpy(buffer, pushBinary, sizeof(pushBinary));
      buffer += sizeof(pushBinary);

      // MOVSD xmm0, source
      //
      *buffer++ = 0xf2;
      if( (*buffer = sourceRegister->rexBits(TR::RealRegister::REX_B, false)) )
         buffer++;
      *buffer++ = 0x0f;
      *buffer++ = 0x10;
      *buffer   = 0xc0;
      sourceRegister->setRegisterFieldInOpcode(buffer);
      buffer++;
      }

   // Call the helper
   //
   buffer = emitCallToConversionHelper(buffer);

   // Restore xmm0 if necessary
   //
   if (sourceReg != TR::RealRegister::xmm0)
      {
      TR_ASSERT(TR::Compiler->target.is64Bit(), "This pop sequence only works on AMD64");
      memcpy(buffer, popBinary, sizeof(popBinary));
      buffer += sizeof(popBinary);
      }

   if (targetReg != TR::RealRegister::eax)
      {
      // XCHG R, rax
      //
      *buffer++ = TR::RealRegister::REX | TR::RealRegister::REX_W | targetRegister->rexBits(TR::RealRegister::REX_B, false);
      *buffer = 0x90;
      targetRegister->setRegisterFieldInOpcode(buffer);
      buffer++;
      }

   return buffer;
   }

void
TR_Debug::print(TR::FILE *pOutFile, TR::AMD64FPConversionSnippet * snippet)
   {

   if (pOutFile == NULL)
      return;

   uint8_t *bufferPos = snippet->getSnippetLabel()->getCodeLocation();

   printSnippetLabel(pOutFile, snippet->getSnippetLabel(), bufferPos, getName(snippet));

   TR::Machine *machine = _cg->machine();
   TR::RealRegister *sourceRegister = toRealRegister(snippet->getConvertInstruction()->getSourceRegister());
   TR::RealRegister *targetRegister = toRealRegister(snippet->getConvertInstruction()->getTargetRegister());
   uint8_t             sreg           = sourceRegister->getRegisterNumber();
   uint8_t             treg           = targetRegister->getRegisterNumber();
   TR::ILOpCodes        opCode         = snippet->getConvertInstruction()->getNode()->getOpCodeValue();
   TR_RegisterSizes    size           = TR_DoubleWordReg;

   if (treg != TR::RealRegister::eax)
      {
      int instrSize = IS_REX(*bufferPos)? 3 : 2;
      printPrefix(pOutFile, NULL, bufferPos, instrSize);
      trfprintf(pOutFile, "mov \t");
      print(pOutFile, targetRegister, size);
      trfprintf(pOutFile, ", ");
      print(pOutFile, machine->getX86RealRegister(TR::RealRegister::eax), size);
      trfprintf(pOutFile, "\t%s preserve helper return reg",
                    commentString());
      bufferPos += instrSize;
      }

   if (sreg != TR::RealRegister::xmm0)
      {
      printPrefix(pOutFile, NULL, bufferPos, 4);
      trfprintf(pOutFile, "sub \trsp, 8");
      printPrefix(pOutFile, NULL, bufferPos, 5);
      trfprintf(pOutFile, "movsd\t[rsp], xmm0\t%s save xmm0",
                    commentString());
      bufferPos += 9;
      int instrSize = IS_REX(*bufferPos)? 5 : 4;
      printPrefix(pOutFile, NULL, bufferPos, instrSize);
      trfprintf(pOutFile, "movsd\txmm0, ");
      print(pOutFile, sourceRegister, TR_QuadWordReg);
      trfprintf(pOutFile, "\t%s load parameter",
                    commentString());
      bufferPos += instrSize;
      }

   printPrefix(pOutFile, NULL, bufferPos, 5);
   trfprintf(pOutFile, "call\t%s", getName(snippet->getHelperSymRef()));
   bufferPos += 5;

   if (sreg != TR::RealRegister::xmm0)
      {
      printPrefix(pOutFile, NULL, bufferPos, 5);
      trfprintf(pOutFile, "movsd\txmm0, [rsp]\t%s restore xmm0",
                    commentString());
      printPrefix(pOutFile, NULL, bufferPos, 4);
      trfprintf(pOutFile, "add \trsp, 8");
      bufferPos += 9;
      }

   if (treg != TR::RealRegister::eax)
      {
      int instrSize = IS_REX(*bufferPos)? 2 : 1;
      printPrefix(pOutFile, NULL, bufferPos, instrSize);
      trfprintf(pOutFile, "xchg\t");
      print(pOutFile, targetRegister, size);
      trfprintf(pOutFile, ", ");
      print(pOutFile, machine->getX86RealRegister(TR::RealRegister::eax), size);
      trfprintf(pOutFile, "\t%s restore result reg & put result in target reg",
                    commentString());
      bufferPos += instrSize;
      }

   printRestartJump(pOutFile, snippet, bufferPos);
   }