本文整理汇总了C++中tr::Machine::reverseSpillState方法的典型用法代码示例。如果您正苦于以下问题：C++ Machine::reverseSpillState方法的具体用法？C++ Machine::reverseSpillState怎么用？C++ Machine::reverseSpillState使用的例子？那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类tr::Machine的用法示例。
在下文中一共展示了Machine::reverseSpillState方法的1个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: assignRegisters
//.........这里部分代码省略.........
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
dependentRegNum = dependencies[i].getRealRegister();
dependentRealReg = machine->getRealRegister(dependentRegNum);
if (dependentRegNum != TR::RealRegister::NoReg &&
dependentRegNum != TR::RealRegister::SpilledReg &&
dependentRealReg->getState() == TR::RealRegister::Free)
{
machine->coerceRegisterAssignment(currentInstruction, virtReg, dependentRegNum);
virtReg->block();
changed = true;
}
}
} while (changed == true);
do
{
changed = false;
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
assignedRegister = NULL;
if (virtReg->getAssignedRealRegister() != NULL)
{
assignedRegister = toRealRegister(virtReg->getAssignedRealRegister());
}
dependentRegNum = dependencies[i].getRealRegister();
dependentRealReg = machine->getRealRegister(dependentRegNum);
if (dependentRegNum != TR::RealRegister::NoReg &&
dependentRegNum != TR::RealRegister::SpilledReg &&
dependentRealReg != assignedRegister)
{
machine->coerceRegisterAssignment(currentInstruction, virtReg, dependentRegNum);
virtReg->block();
changed = true;
}
}
} while (changed == true);
for (i=0; i<numberOfRegisters; i++)
{
if (dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
{
bool excludeGPR0 = dependencies[i].getExcludeGPR0()?true:false;
TR::RealRegister *realOne;
virtReg = dependencies[i].getRegister();
realOne = virtReg->getAssignedRealRegister();
if (realOne!=NULL && excludeGPR0 && toRealRegister(realOne)->getRegisterNumber()==TR::RealRegister::gr0)
{
if ((assignedRegister = machine->findBestFreeRegister(virtReg->getKind(), true)) == NULL)
{
assignedRegister = machine->freeBestRegister(currentInstruction, virtReg->getKind(), NULL, true);
}
machine->coerceRegisterAssignment(currentInstruction, virtReg, assignedRegister->getRegisterNumber());
}
else if (realOne == NULL)
{
if (virtReg->getTotalUseCount() == virtReg->getFutureUseCount())
{
if ((assignedRegister = machine->findBestFreeRegister(virtReg->getKind(), excludeGPR0, true)) == NULL)
{
assignedRegister = machine->freeBestRegister(currentInstruction, virtReg->getKind(), NULL, excludeGPR0);
}
}
else
{
assignedRegister = machine->reverseSpillState(currentInstruction, virtReg, NULL, excludeGPR0);
}
virtReg->setAssignedRegister(assignedRegister);
assignedRegister->setAssignedRegister(virtReg);
assignedRegister->setState(TR::RealRegister::Assigned);
virtReg->block();
}
}
}
unblockRegisters(numberOfRegisters);
for (i = 0; i < numberOfRegisters; i++)
{
TR::Register *dependentRegister = getRegisterDependency(i)->getRegister();
if (dependentRegister->getAssignedRegister())
{
TR::RealRegister *assignedRegister = dependentRegister->getAssignedRegister()->getRealRegister();
if (getRegisterDependency(i)->getRealRegister() == TR::RealRegister::NoReg)
getRegisterDependency(i)->setRealRegister(toRealRegister(assignedRegister)->getRegisterNumber());
if (dependentRegister->decFutureUseCount() == 0)
{
dependentRegister->setAssignedRegister(NULL);
assignedRegister->setAssignedRegister(NULL);
assignedRegister->setState(TR::RealRegister::Unlatched); // Was setting to Free
}
}
}
}