本文整理汇总了C++中tr::Machine::assignOneRegister方法的典型用法代码示例。如果您正苦于以下问题：C++ Machine::assignOneRegister方法的具体用法？C++ Machine::assignOneRegister怎么用？C++ Machine::assignOneRegister使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类tr::Machine的用法示例。
在下文中一共展示了Machine::assignOneRegister方法的3个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: cg
void TR::ARM64Trg1Src2Instruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
{
TR::Machine *machine = cg()->machine();
TR::Register *target1Virtual = getTargetRegister();
TR::Register *source1Virtual = getSource1Register();
TR::Register *source2Virtual = getSource2Register();
if (getDependencyConditions())
getDependencyConditions()->assignPostConditionRegisters(this, kindToBeAssigned, cg());
source1Virtual->block();
target1Virtual->block();
TR::RealRegister *assignedSource2Register = machine->assignOneRegister(this, source2Virtual);
target1Virtual->unblock();
source1Virtual->unblock();
source2Virtual->block();
target1Virtual->block();
TR::RealRegister *assignedSource1Register = machine->assignOneRegister(this, source1Virtual);
target1Virtual->unblock();
source2Virtual->unblock();
source2Virtual->block();
source1Virtual->block();
TR::RealRegister *assignedTarget1Register = machine->assignOneRegister(this, target1Virtual);
source1Virtual->unblock();
source2Virtual->unblock();
if (getDependencyConditions())
getDependencyConditions()->assignPreConditionRegisters(this->getPrev(), kindToBeAssigned, cg());
setTargetRegister(assignedTarget1Register);
setSource1Register(assignedSource1Register);
setSource2Register(assignedSource2Register);
}示例2: getDependencyConditions
void TR::ARM64Trg1Instruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
{
if (getDependencyConditions())
getDependencyConditions()->assignPostConditionRegisters(this, kindToBeAssigned, cg());
TR::Machine *machine = cg()->machine();
TR::Register *targetVirtual = getTargetRegister();
setTargetRegister(machine->assignOneRegister(this, targetVirtual));
if (getDependencyConditions())
getDependencyConditions()->assignPreConditionRegisters(this->getPrev(), kindToBeAssigned, cg());
}示例3: assignRegisters
//.........这里部分代码省略.........
{
assignFreeRegisters(currentInstruction, &_dependencies[i], map, cg);
}
}
// Assign all virtual regs that depend on a specfic real reg that is not free
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = _dependencies[i].getRegister();
assignedRegister = NULL;
if (virtReg->getAssignedRealRegister() != NULL)
{
assignedRegister = toRealRegister(virtReg->getAssignedRealRegister());
}
dependentRegNum = _dependencies[i].getRealRegister();
dependentRealReg = machine->getPPCRealRegister(dependentRegNum);
if (dependentRegNum != TR::RealRegister::NoReg &&
dependentRegNum != TR::RealRegister::SpilledReg &&
dependentRealReg != assignedRegister)
{
bool depsBlocked = false;
switch (_dependencies[i].getRegister()->getKind())
{
case TR_GPR:
depsBlocked = block_gprs;
break;
case TR_FPR:
depsBlocked = block_fprs;
break;
case TR_VRF:
depsBlocked = block_vrfs;
break;
}
assignContendedRegisters(currentInstruction, &_dependencies[i], map, depsBlocked, cg);
}
}
// Assign all virtual regs that depend on NoReg but exclude gr0
for (i=0; i<numberOfRegisters; i++)
{
if (_dependencies[i].getRealRegister() == TR::RealRegister::NoReg && _dependencies[i].getExcludeGPR0())
{
TR::RealRegister *realOne;
virtReg = _dependencies[i].getRegister();
realOne = virtReg->getAssignedRealRegister();
if (realOne!=NULL && toRealRegister(realOne)->getRegisterNumber()==TR::RealRegister::gr0)
{
if ((assignedRegister = machine->findBestFreeRegister(currentInstruction, virtReg->getKind(), true, false, virtReg)) == NULL)
{
assignedRegister = machine->freeBestRegister(currentInstruction, virtReg, NULL, true);
}
machine->coerceRegisterAssignment(currentInstruction, virtReg, assignedRegister->getRegisterNumber());
}
else if (realOne == NULL)
{
machine->assignOneRegister(currentInstruction, virtReg, true);
}
virtReg->block();
}
}
// Assign all virtual regs that depend on NoReg
for (i=0; i<numberOfRegisters; i++)
{
if (_dependencies[i].getRealRegister() == TR::RealRegister::NoReg && !_dependencies[i].getExcludeGPR0())
{
TR::RealRegister *realOne;
virtReg = _dependencies[i].getRegister();
realOne = virtReg->getAssignedRealRegister();
if (!realOne)
{
machine->assignOneRegister(currentInstruction, virtReg, false);
}
virtReg->block();
}
}
unblockRegisters(numberOfRegisters);
for (i = 0; i < numberOfRegisters; i++)
{
TR::Register *dependentRegister = getRegisterDependency(i)->getRegister();
// dependentRegister->getAssignedRegister() is NULL if the reg has already been spilled due to a spilledReg dep
if (comp->getOption(TR_DisableOOL) || (!(cg->isOutOfLineColdPath()) && !(cg->isOutOfLineHotPath())))
{
TR_ASSERT(dependentRegister->getAssignedRegister(),
"assignedRegister can not be NULL");
}
if (dependentRegister->getAssignedRegister())
{
TR::RealRegister *assignedRegister = dependentRegister->getAssignedRegister()->getRealRegister();
if (getRegisterDependency(i)->getRealRegister() == TR::RealRegister::NoReg)
getRegisterDependency(i)->setRealRegister(toRealRegister(assignedRegister)->getRegisterNumber());
machine->decFutureUseCountAndUnlatch(dependentRegister);
}
}
}