C++ iterator::erase方法代码示例

/// fixupLoopInsts - For Hexagon, if the loop label is to far from the
/// loop instruction then we need to set the LC0 and SA0 registers
/// explicitly instead of using LOOP(start,count).  This function
/// checks the distance, and generates register assignments if needed.
///
/// This function makes two passes over the basic blocks.  The first
/// pass computes the offset of the basic block from the start.
/// The second pass checks all the loop instructions.
bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {

  // Offset of the current instruction from the start.
  unsigned InstOffset = 0;
  // Map for each basic block to it's first instruction.
  DenseMap<MachineBasicBlock*, unsigned> BlockToInstOffset;

  // First pass - compute the offset of each basic block.
  for (MachineFunction::iterator MBB = MF.begin(), MBBe = MF.end();
       MBB != MBBe; ++MBB) {
    BlockToInstOffset[MBB] = InstOffset;
    InstOffset += (MBB->size() * 4);
  }

  // Second pass - check each loop instruction to see if it needs to
  // be converted.
  InstOffset = 0;
  bool Changed = false;
  RegScavenger RS;

  // Loop over all the basic blocks.
  for (MachineFunction::iterator MBB = MF.begin(), MBBe = MF.end();
       MBB != MBBe; ++MBB) {
    InstOffset = BlockToInstOffset[MBB];
    RS.enterBasicBlock(MBB);

    // Loop over all the instructions.
    MachineBasicBlock::iterator MIE = MBB->end();
    MachineBasicBlock::iterator MII = MBB->begin();
    while (MII != MIE) {
      if (isHardwareLoop(MII)) {
        RS.forward(MII);
        assert(MII->getOperand(0).isMBB() &&
               "Expect a basic block as loop operand");
        int diff = InstOffset - BlockToInstOffset[MII->getOperand(0).getMBB()];
        diff = (diff > 0 ? diff : -diff);
        if ((unsigned)diff > MAX_LOOP_DISTANCE) {
          // Convert to explicity setting LC0 and SA0.
          convertLoopInstr(MF, MII, RS);
          MII = MBB->erase(MII);
          Changed = true;
        } else {
          ++MII;
        }
      } else {
        ++MII;
      }
      InstOffset += 4;
    }
  }

  return Changed;

}

//.........这里部分代码省略.........
          // Have we already allocated a scratch register for this virtual?
          if (Reg != CurrentVirtReg) {
            // When we first encounter a new virtual register, it
            // must be a definition.
            assert(MI->getOperand(i).isDef() &&
                   "frame index virtual missing def!");
            // We can't have nested virtual register live ranges because
            // there's only a guarantee of one scavenged register at a time.
            assert (CurrentVirtReg == 0 &&
                    "overlapping frame index virtual registers!");

            // If the target gave us information about what's in the register,
            // we can use that to re-use scratch regs.
            DenseMap<unsigned, FrameConstantEntry>::iterator Entry =
              FrameConstantRegMap.find(Reg);
            trackingCurrentValue = Entry != FrameConstantRegMap.end();
            if (trackingCurrentValue) {
              SPAdj = (*Entry).second.second;
              Value = (*Entry).second.first;
            } else {
              SPAdj = 0;
              Value.first = 0;
              Value.second = 0;
            }

            // If the scratch register from the last allocation is still
            // available, see if the value matches. If it does, just re-use it.
            if (trackingCurrentValue && havePrevValue && PrevValue == Value) {
              // FIXME: This assumes that the instructions in the live range
              // for the virtual register are exclusively for the purpose
              // of populating the value in the register. That's reasonable
              // for these frame index registers, but it's still a very, very
              // strong assumption. rdar://7322732. Better would be to
              // explicitly check each instruction in the range for references
              // to the virtual register. Only delete those insns that
              // touch the virtual register.

              // Find the last use of the new virtual register. Remove all
              // instruction between here and there, and update the current
              // instruction to reference the last use insn instead.
              MachineBasicBlock::iterator LastUseMI =
                findLastUseReg(I, BB->end(), Reg);

              // Remove all instructions up 'til the last use, since they're
              // just calculating the value we already have.
              BB->erase(I, LastUseMI);
              I = LastUseMI;

              // Extend the live range of the scratch register
              PrevLastUseMI->getOperand(PrevLastUseOp).setIsKill(false);
              RS->setUsed(CurrentScratchReg);
              CurrentVirtReg = Reg;

              // We deleted the instruction we were scanning the operands of.
              // Jump back to the instruction iterator loop. Don't increment
              // past this instruction since we updated the iterator already.
              DoIncr = false;
              break;
            }

            // Scavenge a new scratch register
            CurrentVirtReg = Reg;
            const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
            CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
            PrevValue = Value;
          }
          // replace this reference to the virtual register with the
          // scratch register.
          assert (CurrentScratchReg && "Missing scratch register!");
          MI->getOperand(i).setReg(CurrentScratchReg);

          if (MI->getOperand(i).isKill()) {
            isKillInsn = true;
            PrevLastUseOp = i;
            PrevLastUseMI = MI;
          }
        }
      }
      // If this is the last use of the scratch, stop tracking it. The
      // last use will be a kill operand in an instruction that does
      // not also define the scratch register.
      if (isKillInsn && !isDefInsn) {
        CurrentVirtReg = 0;
        havePrevValue = trackingCurrentValue;
      }
      // Similarly, notice if instruction clobbered the value in the
      // register we're tracking for possible later reuse. This is noted
      // above, but enforced here since the value is still live while we
      // process the rest of the operands of the instruction.
      if (clobbersScratchReg) {
        havePrevValue = false;
        CurrentScratchReg = 0;
      }
      if (DoIncr) {
        RS->forward(I);
        ++I;
      }
    }
  }
}

bool
MSPUPacketizer::runOnMachineFunction(MachineFunction &Fn)
{
	const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
	MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
	MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();

	// Instantiate the packetizer.
	MSPUPacketizerList Packetizer(Fn, MLI, MDT);

	// DFA state table should not be empty.
	assert(Packetizer.getResourceTracker() && "Empty DFA table!");

	//
	// Loop over all basic blocks and remove KILL pseudo-instructions
	// These instructions confuse the dependence analysis. Consider:
	// D0 = ... 		(Insn 0)
	// R0 = KILL R0, D0 (Insn 1)
	// R0 = ... 		(Insn 2)
	// Here, Insn 1 will result in the dependence graph not emitting an output
	// dependence between Insn 0 and Insn 2. This can lead to incorrect
	// packetization
	//
	for(MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
			MBB != MBBe; ++MBB) {
		MachineBasicBlock::iterator End = MBB->end();
		MachineBasicBlock::iterator MI = MBB->begin();
		while(MI != End) {
			if(MI->isKill()) {
				MachineBasicBlock::iterator DeleteMI = MI;
				++MI;
				MBB->erase(DeleteMI);
				End = MBB->end();
				continue;
			}
			++MI;
		}
	}

	// Loop over all of the basic blocks.
	for(MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
			MBB != MBBe; ++MBB) {
		// Find scheduling regions and schedule / packetize each region.
		unsigned RemainingCount = MBB->size();
		for(MachineBasicBlock::iterator RegionEnd = MBB->end();
				RegionEnd != MBB->begin();) {
			// The next region starts above the previous region. Look backward in the
			// instruction stream until we find the nearest boundary.
			MachineBasicBlock::iterator I = RegionEnd;
			for(; I != MBB->begin(); --I, --RemainingCount) {
				if(TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
					break;
			}
			I = MBB->begin();

			// Skip empty scheduling regions.
			if(I == RegionEnd) {
				RegionEnd = llvm::prior(RegionEnd);
				--RemainingCount;
				continue;
			}
			// Skip regions with one instruction.
			if(I == llvm::prior(RegionEnd)) {
				RegionEnd = llvm::prior(RegionEnd);
				continue;
			}

			// PacketizeMIs() does a VLIW scheduling on MachineInstr list and packetizing.
			Packetizer.PacketizeMIs(MBB, I, RegionEnd);
			RegionEnd = I;
		}
	}

	return true;
}