本文整理汇总了C++中llvm::Triple::getSubArch方法的典型用法代码示例。如果您正苦于以下问题:C++ Triple::getSubArch方法的具体用法?C++ Triple::getSubArch怎么用?C++ Triple::getSubArch使用的例子?那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类llvm::Triple
的用法示例。
在下文中一共展示了Triple::getSubArch方法的5个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: updateRuntimeLibraryPath
static void updateRuntimeLibraryPath(SearchPathOptions &SearchPathOpts,
llvm::Triple &Triple) {
llvm::SmallString<128> LibPath(SearchPathOpts.RuntimeResourcePath);
llvm::sys::path::append(LibPath, getPlatformNameForTriple(Triple));
SearchPathOpts.RuntimeLibraryPath = LibPath.str();
// The linux provided triple for ARM contains a trailing 'l'
// denoting little-endian. This is not used in the path for
// libraries. LLVM matches these SubArchTypes to the generic
// ARMSubArch_v7 (for example) type. If that is the case,
// use the base of the architecture type in the library path.
if (Triple.isOSLinux()) {
switch(Triple.getSubArch()) {
default:
llvm::sys::path::append(LibPath, Triple.getArchName());
break;
case llvm::Triple::SubArchType::ARMSubArch_v7:
llvm::sys::path::append(LibPath, "armv7");
break;
case llvm::Triple::SubArchType::ARMSubArch_v6:
llvm::sys::path::append(LibPath, "armv6");
break;
}
} else {
llvm::sys::path::append(LibPath, Triple.getArchName());
}
SearchPathOpts.RuntimeLibraryImportPath = LibPath.str();
}
示例2: configureARM
/// Configures target-specific information for 32-bit arm platforms.
static void configureARM(IRGenModule &IGM, const llvm::Triple &triple,
SwiftTargetInfo &target) {
// ARM requires marker assembly for objc_retainAutoreleasedReturnValue.
target.ObjCRetainAutoreleasedReturnValueMarker =
"mov\tr7, r7\t\[email protected] marker for objc_retainAutoreleaseReturnValue";
// armv7k has opaque ISAs which must go through the ObjC runtime.
if (triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v7k)
target.ObjCHasOpaqueISAs = true;
}
示例3: getMajorArchitectureName
StringRef swift::getMajorArchitectureName(const llvm::Triple &Triple) {
if (Triple.isOSLinux()) {
switch(Triple.getSubArch()) {
default:
return Triple.getArchName();
break;
case llvm::Triple::SubArchType::ARMSubArch_v7:
return "armv7";
break;
case llvm::Triple::SubArchType::ARMSubArch_v6:
return "armv6";
break;
}
} else {
return Triple.getArchName();
}
}
示例4: switch
// This function maps triples to the architecture component of the path
// where the swift_begin.o and swift_end.o objects can be found. This
// is a stop-gap until full Triple support (ala Clang) exists within swiftc.
StringRef
getSectionMagicArch(const llvm::Triple &Triple) {
if (Triple.isOSLinux()) {
switch(Triple.getSubArch()) {
default:
return Triple.getArchName();
break;
case llvm::Triple::SubArchType::ARMSubArch_v7:
return "armv7";
break;
case llvm::Triple::SubArchType::ARMSubArch_v6:
return "armv6";
break;
}
} else {
return Triple.getArchName();
}
}
示例5: getARMTargetFeatures
//.........这里部分代码省略.........
}
// En/disable crc code generation.
if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) {
if (A->getOption().matches(options::OPT_mcrc))
Features.push_back("+crc");
else
Features.push_back("-crc");
}
// Look for the last occurrence of -mlong-calls or -mno-long-calls. If
// neither options are specified, see if we are compiling for kernel/kext and
// decide whether to pass "+long-calls" based on the OS and its version.
if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
options::OPT_mno_long_calls)) {
if (A->getOption().matches(options::OPT_mlong_calls))
Features.push_back("+long-calls");
} else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6)) &&
!Triple.isWatchOS()) {
Features.push_back("+long-calls");
}
// Generate execute-only output (no data access to code sections).
// This only makes sense for the compiler, not for the assembler.
if (!ForAS) {
// Supported only on ARMv6T2 and ARMv7 and above.
// Cannot be combined with -mno-movt or -mlong-calls
if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, options::OPT_mno_execute_only)) {
if (A->getOption().matches(options::OPT_mexecute_only)) {
if (getARMSubArchVersionNumber(Triple) < 7 &&
llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6T2)
D.Diag(diag::err_target_unsupported_execute_only) << Triple.getArchName();
else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
// Long calls create constant pool entries and have not yet been fixed up
// to play nicely with execute-only. Hence, they cannot be used in
// execute-only code for now
else if (Arg *B = Args.getLastArg(options::OPT_mlong_calls, options::OPT_mno_long_calls)) {
if (B->getOption().matches(options::OPT_mlong_calls))
D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
}
Features.push_back("+execute-only");
}
}
}
// Kernel code has more strict alignment requirements.
if (KernelOrKext)
Features.push_back("+strict-align");
else if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
options::OPT_munaligned_access)) {
if (A->getOption().matches(options::OPT_munaligned_access)) {
// No v6M core supports unaligned memory access (v6M ARM ARM A3.2).
if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
D.Diag(diag::err_target_unsupported_unaligned) << "v6m";
// v8M Baseline follows on from v6M, so doesn't support unaligned memory
// access either.
else if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8m_baseline)
D.Diag(diag::err_target_unsupported_unaligned) << "v8m.base";
} else
Features.push_back("+strict-align");
} else {
// Assume pre-ARMv6 doesn't support unaligned accesses.
//
// ARMv6 may or may not support unaligned accesses depending on the
// SCTLR.U bit, which is architecture-specific. We assume ARMv6
// Darwin and NetBSD targets support unaligned accesses, and others don't.
//
// ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
// which raises an alignment fault on unaligned accesses. Linux
// defaults this bit to 0 and handles it as a system-wide (not
// per-process) setting. It is therefore safe to assume that ARMv7+
// Linux targets support unaligned accesses. The same goes for NaCl.
//
// The above behavior is consistent with GCC.
int VersionNum = getARMSubArchVersionNumber(Triple);
if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
if (VersionNum < 6 ||
Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
Features.push_back("+strict-align");
} else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
if (VersionNum < 7)
Features.push_back("+strict-align");
} else
Features.push_back("+strict-align");
}
// llvm does not support reserving registers in general. There is support
// for reserving r9 on ARM though (defined as a platform-specific register
// in ARM EABI).
if (Args.hasArg(options::OPT_ffixed_r9))
Features.push_back("+reserve-r9");
// The kext linker doesn't know how to deal with movw/movt.
if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
Features.push_back("+no-movt");
if (Args.hasArg(options::OPT_mno_neg_immediates))
Features.push_back("+no-neg-immediates");
}