C++ codeGen::rs方法代码示例

void EmitterAARCH64::emitRelOpImm(
        unsigned opcode, Register dest, Register src1, RegValue src2imm, codeGen &gen, bool s)
{
    //Register src2 = gen.rs()->allocateRegister(gen, true);
    Register src2 = gen.rs()->getScratchRegister(gen);
    emitLoadConst(src2, src2imm, gen);

    // CMP is an alias to SUBS;
    // dest here has src1-src2, which it's not important because the flags are
    // used for the comparison, not the subtration value.
    // Besides that dest must contain 1 for true or 0 for false, and the content
    // of dest is gonna be changed as follow.
    insnCodeGen::generateAddSubShifted(gen, insnCodeGen::Sub, 0, 0, src2, src1, dest, true);

    // make dest = 1, meaning true
    insnCodeGen::loadImmIntoReg<Address>(gen, dest, 0x1);

    // insert conditional jump to skip dest=0 in case the comparison resulted true
    // therefore keeping dest=1
    insnCodeGen::generateConditionalBranch(gen, 8, opcode, s);

    // make dest = 0, in case it fails the branch
    insnCodeGen::loadImmIntoReg<Address>(gen, dest, 0x0);

    gen.rs()->freeRegister(src2);
    gen.markRegDefined(dest);
}

void EmitterAARCH64::emitLoad(Register dest, Address addr, int size, codeGen &gen)
{
    Register scratch = gen.rs()->getScratchRegister(gen);

    insnCodeGen::loadImmIntoReg<Address>(gen, scratch, addr);
    insnCodeGen::generateMemAccess(gen, insnCodeGen::Load, dest,
            scratch, 0, size, insnCodeGen::Post);

    gen.rs()->freeRegister(scratch);
    gen.markRegDefined(dest);
}

void EmitterAARCH64::emitLoadOrigRegRelative(
        Register dest, Address offset, Register base, codeGen &gen, bool deref)
{

    gen.markRegDefined(dest);

    // either load the address or the contents at that address
    if(deref)
    {
        Register scratch = gen.rs()->getScratchRegister(gen);
        assert(scratch);
        gen.markRegDefined(scratch);
        // load the stored register 'base' into scratch
        insnCodeGen::generateMove(gen, scratch, base, true);
        // move offset(%scratch), %dest
        insnCodeGen::generateMemAccess(gen, insnCodeGen::Load, dest,
            scratch, offset, /*size==8?true:false*/4, insnCodeGen::Offset);
    }
    else
    {
        // load the stored register 'base' into dest
        insnCodeGen::generateMove(gen, dest, base, true);
        // add $offset, %dest
        emitImm(plusOp, dest, offset, dest, gen, false);
    }
}

//#sasha Fix parameters number
void EmitterAARCH64::emitGetParam(
        Register dest, Register param_num,
        instPoint::Type pt_type, opCode op,
        bool addr_of, codeGen &gen)
{
    registerSlot *regSlot = NULL;
    switch (op) {
        case getParamOp:
            if(param_num <= 3) {
                // param_num is 0..8 - it's a parameter number, not a register
                regSlot = (*(gen.rs()))[registerSpace::r0 + param_num];
                break;

            } else {
                assert(0);
            }
            break;
        default:
            assert(0);
            break;
    } // end of swich(op)

    assert(regSlot);
    Register reg = regSlot->number;

    //return reg;
}

bool EmitterIA32::emitCallCleanup(codeGen &gen, func_instance *target, 
                     int frame_size, pdvector<Register> &extra_saves)
{
    callType call_conv = target->getCallingConvention();
    if ((call_conv == unknown_call || call_conv == cdecl_call) && frame_size)
    {
        //Caller clean-up
        emitOpRegImm(0, RealRegister(REGNUM_ESP), frame_size, gen); // add esp, frame_size        
    }
 gen.rs()->incStack(-1 * frame_size);

    //Restore extra registers we may have saved when storing parameters in
    // specific registers
    //emitNeededCallRestores(gen, extra_saves);
    return 0;
}

bool IPPatch::apply(codeGen &gen, CodeBuffer *) {
  relocation_cerr << "\t\t IPPatch::apply" << endl;

  // We want to generate addr (as modified) into the appropriate location.
  // TODO get rid of the #ifdef here...

#if defined(arch_x86) || defined(arch_x86_64) 
    GET_PTR(newInsn, gen); 
    
    *newInsn = 0xE8;
    newInsn++;
    unsigned int *temp = (uint32_t *) newInsn;
    *temp = 0;
    newInsn += sizeof(uint32_t);
    SET_PTR(newInsn, gen);
    Address offset = addr - gen.currAddr() + insn->size();
    REGET_PTR(newInsn, gen);
    *newInsn = 0x81;
    newInsn++;
    *newInsn = 0x04;
    newInsn++;
    *newInsn = 0x24;
    newInsn++;
    temp =  (uint32_t *) newInsn;
    *temp = offset;
    newInsn += sizeof(uint32_t);	  

    if (type == Reg) {
      assert(reg != (Register) -1);
      // pop...
      *newInsn++ = static_cast<unsigned char>(0x58 + reg); // POP family
    }
    SET_PTR(newInsn, gen);
#else
    // For dynamic we can do this in-line
    assert(gen.addrSpace()->edit());

    // Must be in LR
    if (reg == -1) reg = registerSpace::lr;
    assert(reg == registerSpace::lr);

    instPoint *point = gen.point();
    // If we do not have a point then we have to invent one
    if (!point || 
	(point->type() != instPoint::PreInsn &&
	 point->insnAddr() != addr)) {
      point = instPoint::preInsn(func, block, addr, insn, true);
    }
    assert(point);
    
    registerSpace *rs = registerSpace::actualRegSpace(point);
    gen.setRegisterSpace(rs);
    
    int stackSize = 0;
    pdvector<Register> freeReg;
    pdvector<Register> excludeReg;
    
    Register scratchPCReg = gen.rs()->getScratchRegister(gen, true);
    excludeReg.push_back(scratchPCReg);
    Register scratchReg = gen.rs()->getScratchRegister(gen, excludeReg, true);
    
    if ((scratchPCReg == REG_NULL) && (scratchReg == REG_NULL)) {
      excludeReg.clear();
      stackSize = insnCodeGen::createStackFrame(gen, 2, freeReg, excludeReg);
      assert(stackSize == 2);
      scratchPCReg = freeReg[0];
      scratchReg = freeReg[1];
      
    } else if (scratchReg == REG_NULL && scratchPCReg != REG_NULL) {
      stackSize = insnCodeGen::createStackFrame(gen, 1, freeReg, excludeReg);
      assert(stackSize == 1);
      scratchReg = freeReg[0];
    } 
    
    //scratchPCReg == NULL && scratchReg != NULL - not a valid case 
    //since getScratchRegister works in order
    
    // relocaAddr may have moved if we added instructions to setup a new stack frame
    Address newRelocAddr = gen.currAddr();
    
    insnCodeGen::generateBranch(gen, gen.currAddr(),  gen.currAddr()+4, true); // blrl
    insnCodeGen::generateMoveFromLR(gen, scratchPCReg); // mflr
    
    Address varOffset = addr - newRelocAddr;
    gen.emitter()->emitCallRelative(scratchReg, varOffset, scratchPCReg, gen);
    insnCodeGen::generateMoveToLR(gen, scratchReg);

    if( stackSize > 0) {
      insnCodeGen::removeStackFrame(gen); 
    }
#endif
    return true;
}

int EmitterIA32::emitCallParams(codeGen &gen, 
                              const pdvector<AstNodePtr> &operands,
                              func_instance *target, 
                              pdvector<Register> &extra_saves, 
                              bool noCost)
{
    callType call_conven = target->getCallingConvention();
    int estimatedFrameSize = 0;
    pdvector <Register> srcs;
    Register ecx_target = REG_NULL, edx_target = REG_NULL;
    Address unused = ADDR_NULL;
    const int num_operands = operands.size();

    switch (call_conven) {
        case unknown_call:
        case cdecl_call:
        case stdcall_call:
          //Push all registers onto stack
          for (unsigned u = 0; u < operands.size(); u++) {
              Register src = REG_NULL;
              Address unused = ADDR_NULL;
              if (!operands[u]->generateCode_phase2( gen, false, unused, src)) assert(0);
              assert(src != REG_NULL);
              srcs.push_back(src);
          }
          break;
    case thiscall_call:
        //Allocate the ecx register for the 'this' parameter
        if (num_operands) {
            //result = gen.rs()->allocateSpecificRegister(gen, REGNUM_ECX, false);
            //if (!result) {
            //    emitNeededCallSaves(gen, REGNUM_ECX, extra_saves);
            //}
            if (!operands[0]->generateCode_phase2(gen, 
                                                  noCost, 
                                                  unused, ecx_target)) assert(0);
        }
        srcs.push_back(Null_Register);
        //Push other registers onto the stack
        for (unsigned u = 1; u < operands.size(); u++) {
              Register src = REG_NULL;
              Address unused = ADDR_NULL;
              if (!operands[u]->generateCode_phase2( gen, false, unused, src)) assert(0);
              assert(src != REG_NULL);
              srcs.push_back(src);
        }     
        break;
    case fastcall_call:
        if (num_operands) {
            //Allocate the ecx register for the first parameter
            //ecx_target = gen.rs()->allocateSpecificRegister(gen, REGNUM_ECX, false);
            //if (!ecx_target) {
            //    emitNeededCallSaves(gen, REGNUM_ECX, extra_saves);
            //}
        }
        if (num_operands > 1) {
            //Allocate the edx register for the second parameter
            //edx_target = gen.rs()->allocateSpecificRegister(gen, REGNUM_EDX, false);
            //if (!edx_target) {
            //    emitNeededCallSaves(gen, REGNUM_EDX, extra_saves);
            //}
        }
        if (num_operands) {
            if (!operands[0]->generateCode_phase2(gen, 
                                                  noCost, 
                                                  unused, ecx_target)) assert(0);
        }
        if (num_operands > 1) {
            if (!operands[1]->generateCode_phase2(gen, 
                                                  noCost, unused, edx_target)) assert(0);
        }
        srcs.push_back(Null_Register);
        srcs.push_back(Null_Register);

        //Push other registers onto the stack
        for (unsigned u = 2; u < operands.size(); u++) {
              Register src = REG_NULL;
              Address unused = ADDR_NULL;
              if (!operands[u]->generateCode_phase2( gen, false, unused, src)) assert(0);
              assert(src != REG_NULL);
              srcs.push_back(src);
        }
        break;
    default:
        fprintf(stderr, "Internal error.  Unknown calling convention\n");
        assert(0);
    }

    // push arguments in reverse order, last argument first
    // must use int instead of unsigned to avoid nasty underflow problem:
    for (int i=srcs.size() - 1; i >= 0; i--) {
       if (srcs[i] == Null_Register) continue;
	   RealRegister r = gen.rs()->loadVirtual(srcs[i], gen);
	   ::emitPush(r, gen);
       estimatedFrameSize += 4;
       if (operands[i]->decRefCount())
          gen.rs()->freeRegister(srcs[i]);
    }

    if (ecx_target != REG_NULL) {
//.........这里部分代码省略.........