本文整理汇总了C++中Signal::toVHDL方法的典型用法代码示例。如果您正苦于以下问题：C++ Signal::toVHDL方法的具体用法？C++ Signal::toVHDL怎么用？C++ Signal::toVHDL使用的例子？那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类Signal的用法示例。
在下文中一共展示了Signal::toVHDL方法的2个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: outputVHDLEntity
void Operator::outputVHDLEntity(std::ostream& o) {
unsigned int i;
if(isSequential() && getClkName().compare("") == 0) {
std::cerr << "-- Can't find clock port for sequential component" << std::endl;
}
o << "entity " << uniqueName_ << " is" << endl;
if (ioList_.size() > 0)
{
o << tab << "port ( " << endl;
/*
if(isSequential()) {
o << getClkName() << " : in std_logic;" <<endl;
std::string rst = getRstName();
if (rst.compare("") != 0) {
o << rst << " : in std_logic;" <<endl;
}
}
*/
for (i=0; i<this->ioList_.size(); i++){
Signal* s = this->ioList_[i];
// if (i>0 || isSequential()) // align signal names
// o<<" ";
o<< tab << tab << tab << s->toVHDL();
if(i < this->ioList_.size()-1) o<<";" << endl;
}
o << endl << tab << ");"<<endl;
}
o << "end entity;" << endl << endl;
}示例2: outputVHDLSignalDeclarations
void Operator::outputVHDLSignalDeclarations(std::ostream& o) {
for (unsigned int i=0; i < this->signalList_.size(); i++){
Signal* s = this->signalList_[i];
o<<tab<< s->toVHDL() << ";" << endl;
}
}