C++ OpArg::IsImm方法代码示例

void EmuCodeBlock::UnsafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int accessSize, s32 offset,
                                       bool swap, MovInfo* info)
{
  if (info)
  {
    info->address = GetWritableCodePtr();
    info->nonAtomicSwapStore = false;
  }

  OpArg dest = MComplex(RMEM, reg_addr, SCALE_1, offset);
  if (reg_value.IsImm())
  {
    if (swap)
      reg_value = SwapImmediate(accessSize, reg_value);
    MOV(accessSize, dest, reg_value);
  }
  else if (swap)
  {
    SwapAndStore(accessSize, dest, reg_value.GetSimpleReg(), info);
  }
  else
  {
    MOV(accessSize, dest, reg_value);
  }
}

bool EmuCodeBlock::UnsafeLoadToReg(X64Reg reg_value, OpArg opAddress, int accessSize, s32 offset,
                                   bool signExtend, MovInfo* info)
{
  bool offsetAddedToAddress = false;
  OpArg memOperand;
  if (opAddress.IsSimpleReg())
  {
    // Deal with potential wraparound.  (This is just a heuristic, and it would
    // be more correct to actually mirror the first page at the end, but the
    // only case where it probably actually matters is JitIL turning adds into
    // offsets with the wrong sign, so whatever.  Since the original code
    // *could* try to wrap an address around, however, this is the correct
    // place to address the issue.)
    if ((u32)offset >= 0x1000)
    {
      // This method can potentially clobber the address if it shares a register
      // with the load target. In this case we can just subtract offset from the
      // register (see Jit64Base for this implementation).
      offsetAddedToAddress = (reg_value == opAddress.GetSimpleReg());

      LEA(32, reg_value, MDisp(opAddress.GetSimpleReg(), offset));
      opAddress = R(reg_value);
      offset = 0;
    }
    memOperand = MComplex(RMEM, opAddress.GetSimpleReg(), SCALE_1, offset);
  }
  else if (opAddress.IsImm())
  {
    MOV(32, R(reg_value), Imm32((u32)(opAddress.Imm32() + offset)));
    memOperand = MRegSum(RMEM, reg_value);
  }
  else
  {
    MOV(32, R(reg_value), opAddress);
    memOperand = MComplex(RMEM, reg_value, SCALE_1, offset);
  }

  LoadAndSwap(accessSize, reg_value, memOperand, signExtend, info);
  return offsetAddedToAddress;
}

void Jit64::cmpXX(UGeckoInstruction inst)
{
	// USES_CR
	INSTRUCTION_START
	JITDISABLE(bJITIntegerOff);
	int a = inst.RA;
	int b = inst.RB;
	int crf = inst.CRFD;

	bool merge_branch = false;
	int test_crf = js.next_inst.BI >> 2;
	// Check if the next instruction is a branch - if it is, merge the two.
	if (((js.next_inst.OPCD == 16 /* bcx */) ||
	    ((js.next_inst.OPCD == 19) && (js.next_inst.SUBOP10 == 528) /* bcctrx */) ||
	    ((js.next_inst.OPCD == 19) && (js.next_inst.SUBOP10 == 16) /* bclrx */)) &&
	    (js.next_inst.BO & BO_DONT_DECREMENT_FLAG) &&
	    !(js.next_inst.BO & BO_DONT_CHECK_CONDITION))
	{
			// Looks like a decent conditional branch that we can merge with.
			// It only test CR, not CTR.
			if (test_crf == crf)
			{
				merge_branch = true;
			}
	}

	OpArg comparand;
	bool signedCompare;
	if (inst.OPCD == 31)
	{
		// cmp / cmpl
		gpr.Lock(a, b);
		comparand = gpr.R(b);
		signedCompare = (inst.SUBOP10 == 0);
	}
	else
	{
		gpr.Lock(a);
		if (inst.OPCD == 10)
		{
			//cmpli
			comparand = Imm32((u32)inst.UIMM);
			signedCompare = false;
		}
		else if (inst.OPCD == 11)
		{
			//cmpi
			comparand = Imm32((u32)(s32)(s16)inst.UIMM);
			signedCompare = true;
		}
		else
		{
			signedCompare = false; // silence compiler warning
			PanicAlert("cmpXX");
		}
	}

	if (gpr.R(a).IsImm() && comparand.IsImm())
	{
		// Both registers contain immediate values, so we can pre-compile the compare result
		u8 compareResult;
		if (signedCompare)
		{
			if ((s32)gpr.R(a).offset == (s32)comparand.offset)
				compareResult = CR_EQ;
			else if ((s32)gpr.R(a).offset > (s32)comparand.offset)
				compareResult = CR_GT;
			else
				compareResult = CR_LT;
		}
		else
		{
			if ((u32)gpr.R(a).offset == (u32)comparand.offset)
				compareResult = CR_EQ;
			else if ((u32)gpr.R(a).offset > (u32)comparand.offset)
				compareResult = CR_GT;
			else
				compareResult = CR_LT;
		}
		MOV(64, R(RAX), Imm64(PPCCRToInternal(compareResult)));
		MOV(64, M(&PowerPC::ppcState.cr_val[crf]), R(RAX));
		gpr.UnlockAll();

		if (merge_branch)
		{
			js.downcountAmount++;
			js.skipnext = true;

			int test_bit = 8 >> (js.next_inst.BI & 3);
			u8 conditionResult = (js.next_inst.BO & BO_BRANCH_IF_TRUE) ? test_bit : 0;
			if ((compareResult & test_bit) == conditionResult)
			{
				gpr.Flush();
				fpr.Flush();

				if (js.next_inst.OPCD == 16) // bcx
				{
					if (js.next_inst.LK)
						MOV(32, M(&LR), Imm32(js.compilerPC + 4));

//.........这里部分代码省略.........

void DSPJitRegCache::putReg(int reg, bool dirty)
{
    int real_reg = reg;
    if (regs[reg].parentReg != DSP_REG_NONE)
        real_reg = regs[reg].parentReg;

    OpArg oparg = regs[real_reg].loc;

    switch (reg)
    {
    case DSP_REG_ACH0:
    case DSP_REG_ACH1:
        if (dirty)
        {
            // no need to extend to full 64bit here until interpreter
            // uses that
            if (oparg.IsSimpleReg())
            {
                // register is already shifted correctly
                // (if at all)

                // sign extend from the bottom 8 bits.
                emitter.MOVSX(16, 8, oparg.GetSimpleReg(), oparg);
            }
            else if (oparg.IsImm())
            {
                // TODO: Immediates?
            }
            else
            {
                // this works on the memory, so use reg instead
                // of real_reg, since it has the right loc
                X64Reg tmp;
                getFreeXReg(tmp);
                // sign extend from the bottom 8 bits.
                emitter.MOVSX(16, 8, tmp, regs[reg].loc);
                emitter.MOV(16, regs[reg].loc, R(tmp));
                putXReg(tmp);
            }
        }
        break;
    case DSP_REG_ACC0_64:
    case DSP_REG_ACC1_64:
        if (dirty)
        {
            emitter.SHL(64, oparg, Imm8(64-40)); // sign extend
            emitter.SAR(64, oparg, Imm8(64-40));
        }
        break;
    default:
        break;
    }

    regs[real_reg].used = false;

    if (regs[real_reg].loc.IsSimpleReg())
    {
        regs[real_reg].dirty |= dirty;
        regs[real_reg].last_use_ctr = use_ctr;
        use_ctr++;
    }
}