C++ Gate::getType方法代码示例

void MyContactListener::BeginContact(b2Contact* contact) {
    b2Body * bodyA = contact->GetFixtureA()->GetBody();
    b2Body * bodyB = contact->GetFixtureB()->GetBody();
    
    b2Sprite * spriteA = (b2Sprite *) bodyA->GetUserData();
    b2Sprite * spriteB = (b2Sprite *) bodyB->GetUserData();
    
    if (spriteA && spriteB) 
	{
		Gate *gate = NULL;
        Ball *b = NULL;
        
		if (kSpriteFootballer == spriteA->getSpriteType() ||
			kSpriteFootballer == spriteB->getSpriteType())
		{
			SimpleAudioEngine::sharedEngine()->playEffect(BALL_SOUND);

			return;
		}

		if (kSpriteGate == spriteA->getSpriteType()) 
		{
			gate = (Gate*)spriteA;
			b = (Ball*)spriteB;
		} 
		else if (kSpriteGate == spriteB->getSpriteType()) 
		{
            gate = (Gate*)spriteB;
            b = (Ball*)spriteA;
		}
        
		if(NULL != gate){
			
            if (NULL != b)
            {
				if (gate->getType() == kRight && b->getPosition().x > (gate->getPositionX() - gate->boundingBox().size.width / 2))
				{
	                gate->setHoldsBall(true);
				}
				else if (gate->getType() == kLeft && b->getPosition().x < (gate->getPositionX() + gate->boundingBox().size.width / 2))
				{
					gate->setHoldsBall(true);
				}
            }
        }
	}
}

void CircuitBuilder::levelize() {
    bool processed[cir_->nGates()];
    bool levelized[cir_->nGates()];
    memset(processed, false, sizeof(bool) * cir_->nGates());
    memset(levelized, false, sizeof(bool) * cir_->nGates());
    for (size_t i = 0; i < cir_->nGates(); ++i)
        cir_->getGate(i)->setId(i);

    queue<Gate *> que;
    for (size_t i = 0; i < cir_->nPis() + cir_->nSeqs(); ++i)
        que.push(cir_->getGate(i));

    while (!que.empty()) {
        Gate *g = que.front();
        que.pop();

        int maxlvl = -1;
        bool ready = true;

        // determine level only if all fanins are levelized
        // 1. PPI is set to level zero 
        // 2. PPI has input PPO
        // 3. Skip PPI directly
        if(g->getType() != Gate::PPI){
            for (size_t i = 0; i < g->nFis(); ++i) {
                Gate *fi = g->getFi(i);
                if (!levelized[fi->getId()]) {
                    ready = false;
                    break;
                }
                if (fi->getLvl() > maxlvl)
                    maxlvl = fi->getLvl();
            }
        }
        // put back to queue if not ready
        if (!ready) {
            que.push(g);
            continue;
        }

        // set level
        g->setLvl(maxlvl + 1);
        levelized[g->getId()] = true;

        // determine circuit level
        if ((g->getType() == Gate::PO || g->getType() == Gate::PPO)
            && g->getLvl() > cir_->getLvl())
            cir_->setLvl(g->getLvl());

        // put fanouts into queue
        for (size_t i = 0; i < g->nFos(); ++i) {
            Gate *fo = g->getFo(i);
            if (processed[fo->getId()])
                continue;
            processed[fo->getId()] = true;
            que.push(fo);
        }
    }

    // set all POs to highest level
    for (size_t i = 0; i < cir_->nPos(); ++i)
        cir_->getPo(i)->setLvl(cir_->getLvl());
    for (size_t i = 0; i < cir_->nSeqs(); ++i)
        cir_->getPpo(i)->setLvl(cir_->getLvl());
    cir_->setLvl(cir_->getLvl() + 1);

    // sort gates by their level
    stable_sort(cir_->getGates()->begin()
        , cir_->getGates()->end()
        , cmpGateLvl);

    // set gate id
    for (size_t i = 0; i < cir_->nGates(); ++i)
        cir_->getGate(i)->setId(i);
}

void CircuitBuilder::build(Design * const design, const size_t &f) {
    delete cir_;
    cir_ = new Circuit;
    cir_->setFrame(f);
    cir_->setOccRoot(design->getOcc());
    cir_->setModRoot(design->getTop());
    map<string,Gate*> FFMap;    // flip-flop map, used to connecte PPI & PPO
    // create PI
    // ignore CK, test_si, and test_so
    for (size_t i = 0; i < design->getTop()->nModTerms(); ++i) {
        ModTerm *term = design->getTop()->getModTerm(i);
        if (term->getType() != ModTerm::INPUT 
            || strcmp(term->getName(),"test_si") == 0 
            || strcmp(term->getName(),"test_se") == 0
            || strcmp(term->getName(),"CK") == 0 )
            continue;
        Gate *g = new PiGate;
        g->setOcc(design->getOcc());
        cir_->addPi(g);
    }

    // create PPI
    for (size_t i = 0; i < design->getOcc()->nChildren(); ++i) {
        Occ *occ = design->getOcc()->getChild(i);
        string modName(occ->getModInst()->getModName());
        if (modName.size() < 4 || modName.substr(0,4) != "SDFF")
            continue;
        Gate *g = new PpiGate;
        g->setOcc(occ);
        cir_->addPpi(g);
        cir_->setOccToGate(occ, g);
        FFMap[occ->getModInst()->getName()] = g;
    }

    // create combinational gates
    for (size_t i = 0; i < design->getOcc()->nChildren(); ++i) {
        Occ *occ = design->getOcc()->getChild(i);
        string modName(occ->getModInst()->getModName());
        if (modName.size() > 3 && modName.substr(0,4) == "SDFF")
            continue;
        Gate *g = createGate(occ);
        g->setOcc(occ);
        cir_->addComb(g);
        cir_->setOccToGate(occ, g);
    }

    // create PO
    for (size_t i = 0; i < design->getTop()->nModTerms(); ++i) {
        ModTerm *term = design->getTop()->getModTerm(i);
        if (term->getType() != ModTerm::OUTPUT)
            continue;
        Gate *g = new PoGate;
        g->setOcc(design->getOcc());
        cir_->addPo(g);
    }

    // create PPO
    for (size_t i = 0; i < design->getOcc()->nChildren(); ++i) {
        Occ *occ = design->getOcc()->getChild(i);
        string modName(occ->getModInst()->getModName());
        if (modName.size() < 4 || modName.substr(0,4) != "SDFF")
            continue;
        Gate *g = new PpoGate;
        g->setOcc(occ);
        cir_->addPpo(g);
        FFMap[occ->getModInst()->getName()]->addFi(g);
    }

    // connect gates
    for (size_t i = cir_->nPis() + cir_->nSeqs(); i < cir_->nGates(); ++i) {
        Gate *g = cir_->getGate(i);
        Occ *occ = g->getOcc();
        size_t nTerm = 0;
        if (g->getType() == Gate::PO || g->getType() == Gate::PPO)
            nTerm = 1;
        else
            nTerm = occ->getModInst()->nModInstTerms() - 1;
        for (size_t j = 0; j < nTerm; ++j) {
            ModTerm *term = NULL;
            ModInstTerm *instTerm = NULL;
            ModNet *net = NULL;
            if (g->getType() == Gate::PO) {
                // because we ignore 3 inputs(CK,test_si,test_so)
                // we have to add 3 in idx to match id in ModTerm
                size_t id = i - cir_->nCombs() - cir_->nSeqs() + 3;
                term = design->getTop()->getModTerm(id);
                net = term->getModNet();
            }
            else if (g->getType() == Gate::PPO) {
                instTerm = occ->getModInst()->getModInstTerm("D");
                net = instTerm->getModNet();
            }
            else {
                instTerm = occ->getModInst()->getModInstTerm(j);
                net = instTerm->getModNet();
            }

            // find fanin
            Gate *fi = NULL;
            for (size_t k = 0; k < net->nModTerms(); ++k) {
//.........这里部分代码省略.........

//Multi-Layer Construction
//J-You class must change to multiple WireList & GateList
//
void CirMgr::multi_Layer(size_t Layer=0){
	//TODO input the longest route
	size_t layerSize = Layer;
	size_t wireSize = WireList[0].size();
	size_t gateSize = GateList[0].size();
	size_t inputSize = InputList[0].size();
	size_t outputSize = OutputList[0].size();
	for(size_t i=0; i<layerSize; ++i){
		//i is previous levelu
		//i+1 is current level
		vector<Wire*> currentWireList;
		vector<Gate*> currentGateList;
		vector<Wire*> currentInputList;
		int in0, in1, out;
		for(size_t j=0; j<wireSize; ++j){	
			Wire* wire = new Wire(WireList[i][j]->getId());
			wire->setListNum(j);
			currentWireList.push_back(wire);
			/*if(j>=inputSize && j<outputSize+inputSize){
				currentWireList.push_back(wire);
			}*/
		}
        #ifdef DEBUG
        cerr << "constuct a layer, new current WireList[i]" << endl;
        #endif

		//input of newer
		if(i == 0){
			for(size_t k=0; k<inputSize; ++k){
				currentWireList[k]->setFin(0);
				currentInputList.push_back(currentWireList[k]);
			}
			InputList.push_back(currentInputList);
		}
        
        #ifdef DEBUG
        if(i==0){
        	cerr<< " Second layer input = " << endl;
            for(size_t j=0 ; j<inputSize ; ++j){
                cerr << currentInputList[j]->getId() << " ";
            }
        }
        #endif
		//gate implement
		for(size_t j=0; j<gateSize; ++j){
			Gate* gate = new Gate(GateList[i][j]->getType(),GateList[i][j]->getId(),0,0,0);
			#ifdef DEBUG
            cerr << "new Gate in gateList["<<i<<"][" << j << "] --FINISHED..." << endl;
            #endif

			in0 = GateList[i][j]->getFin0VecNum();
			out = GateList[i][j]->getFoutVecNum();
			if(in0<(int)inputSize){
				gate->setFin0(InputList[1][in0]);
				InputList[1][in0]->addFout(gate);
			}
			else{
				gate->setFin0(WireList[i][in0]);
				WireList[i][in0]->addFout(gate);
			}
			gate->setFout(currentWireList[out]);
			currentWireList[out]->setFin(gate);
			if(gate->getType()!="NOT1"){
				in1 = GateList[i][j]->getFin1VecNum();
				if(in1<(int)inputSize){
					gate->setFin1(InputList[1][in1]);
					InputList[1][in1]->addFout(gate);
				}
				else{
					gate->setFin1(WireList[i][in1]);
					WireList[i][in1]->addFout(gate);
				}
                setVNum(gate,out,in0,in1);
			}
			else{
                setVNum(gate,out,in0);
			}
			currentGateList.push_back(gate);
		}
		WireList.push_back(currentWireList);
		GateList.push_back(currentGateList);
	}
	#ifdef DEBUG
    cerr <<"Check All Gate"<< endl;
    
	for(size_t i=0;i<layerSize;++i){
		cerr<<"\n*********LAYER "<<i<<"*********\n"<<endl;
		for(size_t j=0;j<gateSize;++j){
			checkGate(GateList[i][j]);	
		}
	}
	#endif	
}