Python pcbnew.F_Cu方法代码示例

# 需要导入模块: import pcbnew [as 别名]
# 或者: from pcbnew import F_Cu [as 别名]
def build(self, center_x, center_y, radius, keepout, edge_count):
        sp = pcbnew.SHAPE_POLY_SET()
        sp.NewOutline()
        cnt = int(edge_count)
        for i in range(cnt):
            x = int(center_x + radius * cos(i * 2 * pi / cnt))
            y = int(center_y + radius * sin(i * 2 * pi / cnt))
            sp.Append(x, y)
        # sp.OutlineCount()
        sp.thisown = 0
        zone = pcbnew.ZONE_CONTAINER(self.pcb)
        zone.SetOutline(sp)
        zone.SetLayer(pcbnew.F_Cu)
        zone.SetIsKeepout(keepout)
        zone.thisown = 0
        self.pcb.Add(zone) 

# 需要导入模块: import pcbnew [as 别名]
# 或者: from pcbnew import F_Cu [as 别名]
def parse_zones(self, zones):
        result = {pcbnew.F_Cu: [], pcbnew.B_Cu: []}
        for zone in zones:  # type: pcbnew.ZONE_CONTAINER
            if not zone.IsFilled() or zone.GetIsKeepout():
                continue
            if zone.GetLayer() in [pcbnew.F_Cu, pcbnew.B_Cu]:
                zone_dict = {
                    "polygons": self.parse_poly_set(zone.GetFilledPolysList()),
                    "width": zone.GetMinThickness() * 1e-6,
                }
                if self.config.include_nets:
                    zone_dict["net"] = zone.GetNetname()
                result[zone.GetLayer()].append(zone_dict)

        return {
            'F': result.get(pcbnew.F_Cu),
            'B': result.get(pcbnew.B_Cu)
        } 

# 需要导入模块: import pcbnew [as 别名]
# 或者: from pcbnew import F_Cu [as 别名]
def module_to_component(module):
        # type: (pcbnew.MODULE) -> Component
        try:
            footprint = str(module.GetFPID().GetFootprintName())
        except AttributeError:
            footprint = str(module.GetFPID().GetLibItemName())

        attr = module.GetAttributes()
        attr = {
            0: 'Normal',
            1: 'Normal+Insert',
            2: 'Virtual'
        }.get(attr, str(attr))
        layer = {
            pcbnew.F_Cu: 'F',
            pcbnew.B_Cu: 'B',
        }.get(module.GetLayer())

        return Component(module.GetReference(),
                         module.GetValue(),
                         footprint,
                         layer,
                         attr) 

# 需要导入模块: import pcbnew [as 别名]
# 或者: from pcbnew import F_Cu [as 别名]
def parse_tracks(self, tracks):
        result = {pcbnew.F_Cu: [], pcbnew.B_Cu: []}
        for track in tracks:
            if track.GetClass() == "VIA":
                track_dict = {
                    "start": self.normalize(track.GetStart()),
                    "end": self.normalize(track.GetEnd()),
                    "width": track.GetWidth() * 1e-6,
                    "net": track.GetNetname(),
                }
                for l in [pcbnew.F_Cu, pcbnew.B_Cu]:
                    if track.IsOnLayer(l):
                        result[l].append(track_dict)
            else:
                if track.GetLayer() in [pcbnew.F_Cu, pcbnew.B_Cu]:
                    track_dict = {
                        "start": self.normalize(track.GetStart()),
                        "end": self.normalize(track.GetEnd()),
                        "width": track.GetWidth() * 1e-6,
                    }
                    if self.config.include_nets:
                        track_dict["net"] = track.GetNetname()
                    result[track.GetLayer()].append(track_dict)

        return {
            'F': result.get(pcbnew.F_Cu),
            'B': result.get(pcbnew.B_Cu)
        } 

# 需要导入模块: import pcbnew [as 别名]
# 或者: from pcbnew import F_Cu [as 别名]
def _get_layer_from_str(self, s):
        """
        Get the pcbnew layer from a string in the config
        """

        D = {
            'F.Cu': pcbnew.F_Cu,
            'B.Cu': pcbnew.B_Cu,
            'F.Adhes': pcbnew.F_Adhes,
            'B.Adhes': pcbnew.B_Adhes,
            'F.Paste': pcbnew.F_Paste,
            'B.Paste': pcbnew.B_Paste,
            'F.SilkS': pcbnew.F_SilkS,
            'B.SilkS': pcbnew.B_SilkS,
            'F.Mask': pcbnew.F_Mask,
            'B.Mask': pcbnew.B_Mask,
            'Dwgs.User': pcbnew.Dwgs_User,
            'Cmts.User': pcbnew.Cmts_User,
            'Eco1.User': pcbnew.Eco1_User,
            'Eco2.User': pcbnew.Eco2_User,
            'Edge.Cuts': pcbnew.Edge_Cuts,
            'Margin': pcbnew.Margin,
            'F.CrtYd': pcbnew.F_CrtYd,
            'B.CrtYd': pcbnew.B_CrtYd,
            'F.Fab': pcbnew.F_Fab,
            'B.Fab': pcbnew.B_Fab,
        }

        layer = None

        if s in D:
            layer = PC.LayerInfo(D[s], False)
        elif s.startswith("Inner"):
            m = re.match(r"^Inner\.([0-9]+)$", s)

            if not m:
                raise YamlError("Malformed inner layer name: {}"
                                .format(s))

            layer = PC.LayerInfo(int(m.group(1)), True)
        else:
            raise YamlError("Unknown layer name: {}".format(s))

        return layer 

# 需要导入模块: import pcbnew [as 别名]
# 或者: from pcbnew import F_Cu [as 别名]
def get_board_substrate(board, colors, holes, back):
    """
    Plots all front layers from the board and arranges them in a visually appealing style.
    return SVG g element with the board substrate
    """
    toPlot = []
    if(back):
        toPlot = [
            ("board", [pcbnew.Edge_Cuts], process_board_substrate_base),
            ("clad", [pcbnew.B_Mask], process_board_substrate_layer),
            ("copper", [pcbnew.B_Cu], process_board_substrate_layer),
            ("pads", [pcbnew.B_Cu], process_board_substrate_layer),
            ("pads-mask", [pcbnew.B_Mask], process_board_substrate_mask),
            ("silk", [pcbnew.B_SilkS], process_board_substrate_layer),
            ("outline", [pcbnew.Edge_Cuts], process_board_substrate_layer)]
    else:
        toPlot = [
            ("board", [pcbnew.Edge_Cuts], process_board_substrate_base),
            ("clad", [pcbnew.F_Mask], process_board_substrate_layer),
            ("copper", [pcbnew.F_Cu], process_board_substrate_layer),
            ("pads", [pcbnew.F_Cu], process_board_substrate_layer),
            ("pads-mask", [pcbnew.F_Mask], process_board_substrate_mask),
            ("silk", [pcbnew.F_SilkS], process_board_substrate_layer),
            ("outline", [pcbnew.Edge_Cuts], process_board_substrate_layer)]
    container = etree.Element('g')
    container.attrib["clip-path"] = "url(#cut-off)"
    tmp = tempfile.mkdtemp()
    pctl = pcbnew.PLOT_CONTROLLER(board)
    popt = pctl.GetPlotOptions()
    popt.SetOutputDirectory(tmp)
    popt.SetScale(1)
    popt.SetMirror(False)
    popt.SetSubtractMaskFromSilk(True)
    try:
        popt.SetPlotOutlineMode(False)
    except:
        # Method does not exist in older versions of KiCad
        pass
    popt.SetTextMode(pcbnew.PLOTTEXTMODE_STROKE)
    for f, layers, _ in toPlot:
        pctl.OpenPlotfile(f, pcbnew.PLOT_FORMAT_SVG, f)
        for l in layers:
            pctl.SetColorMode(False)
            pctl.SetLayer(l)
            pctl.PlotLayer()
    pctl.ClosePlot()
    boardsize = board.ComputeBoundingBox()
    for f, _, process in toPlot:
        for svg_file in os.listdir(tmp):
            if svg_file.endswith("-" + f + ".svg"):
                process(container, f, os.path.join(tmp, svg_file), colors, boardsize)
    shutil.rmtree(tmp)

    if holes:
        container.append(get_hole_mask(board))
        container.attrib["mask"] = "url(#hole-mask)"
    return container 

# 需要导入模块: import pcbnew [as 别名]
# 或者: from pcbnew import F_Cu [as 别名]
def solderExpander(pcb,tracks,clearance):
        mask_width = clearance #FromMM(.5) # msk espansion value each side
        #mask_layer = pcbnew.F_Mask
        
        # pcb = LoadBoard(in_filename)
        #pcb = pcbnew.GetBoard() 
        
        ToUnits=pcbnew.ToMM #ToMils
        FromUnits=pcbnew.FromMM #Mils
        
        for item in tracks:
            start = item.GetStart()
            end = item.GetEnd()
            width = item.GetWidth()
            layerId = item.GetLayer()
            layer = item.GetLayerSet()
            layerN = item.GetLayerName()
            layer = pcb.GetLayerID(layerN)
            track_net_name = item.GetNetname()
            ts = 0
            for c in track_net_name:
                ts = ts + ord(c)
            #wx.LogMessage("LayerName"+str(layer))

            if layerId == pcbnew.F_Cu:
                mask_layer = pcbnew.F_Mask
            elif layerId == pcbnew.B_Cu: #'B_Cu':
                mask_layer = pcbnew.B_Mask
            else: #we shouldn't arrive here
                mask_layer = pcbnew.F_Mask
            wxLogDebug(" * Track: %s to %s, width %f mask_width %f" % (ToUnits(start),ToUnits(end),ToUnits(width), ToUnits(mask_width)),debug)
            #print (" * Track: %s to %s, width %f mask_width %f" % (ToUnits(start),ToUnits(end),ToUnits(width), ToUnits(mask_width)))
            new_soldermask_line = pcbnew.DRAWSEGMENT(pcb)
            new_soldermask_line.SetStart(start)
            new_soldermask_line.SetEnd(end)
            new_soldermask_line.SetWidth(width+2*mask_width) #FromUnits(int(mask_width)))
            new_soldermask_line.SetLayer(mask_layer) #pcbnew.F_Mask) #pcb.GetLayerID(mask_layer))
            # again possible to mark via as own since no timestamp_t binding kicad v5.1.4
            if hasattr(new_soldermask_line, 'SetTimeStamp'):
                new_soldermask_line.SetTimeStamp(ts)  # adding a unique number (this netname) as timestamp to mark this via as generated by this script on this netname
            pcb.Add(new_soldermask_line)
            #break;
        pcbnew.Refresh()        
#