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Python VHDLDesignFile.parse方法代码示例

本文整理汇总了Python中vunit.vhdl_parser.VHDLDesignFile.parse方法的典型用法代码示例。如果您正苦于以下问题:Python VHDLDesignFile.parse方法的具体用法?Python VHDLDesignFile.parse怎么用?Python VHDLDesignFile.parse使用的例子?那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在vunit.vhdl_parser.VHDLDesignFile的用法示例。


在下文中一共展示了VHDLDesignFile.parse方法的10个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的Python代码示例。

示例1: parse_single_context

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
 def parse_single_context(self, code):
     """
     Helper function to parse a single context
     """
     design_file = VHDLDesignFile.parse(code)
     self.assertEqual(len(design_file.contexts), 1)
     return design_file.contexts[0]
开发者ID:jonasalowersson,项目名称:vunit,代码行数:9,代码来源:test_vhdl_parser.py

示例2: parse_single_package_body

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
 def parse_single_package_body(self, code):
     """
     Helper function to parse a single package body
     """
     design_file = VHDLDesignFile.parse(code)
     self.assertEqual(len(design_file.package_bodies), 1)
     return design_file.package_bodies[0]
开发者ID:jonasalowersson,项目名称:vunit,代码行数:9,代码来源:test_vhdl_parser.py

示例3: test_getting_component_instantiations_from_design_file

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
    def test_getting_component_instantiations_from_design_file(self):
        design_file = VHDLDesignFile.parse("""
entity top is
end entity;

architecture arch of top is
begin
    labelFoo : component foo
    generic map(WIDTH => 16)
    port map(clk => '1',
             rst => '0',
             in_vec => record_reg.input_signal,
             output => some_signal(UPPER_CONSTANT-1 downto LOWER_CONSTANT+1));

    label2Foo : foo2
    port map(clk => '1',
             rst => '0',
             output => "00");

    label3Foo : foo3 port map (clk, rst, X"A");

end architecture;

""")
        component_instantiations = design_file.component_instantiations
        self.assertEqual(len(component_instantiations), 3)
        self.assertEqual(component_instantiations[0], "foo")
        self.assertEqual(component_instantiations[1], "foo2")
        self.assertEqual(component_instantiations[2], "foo3")
开发者ID:jonasalowersson,项目名称:vunit,代码行数:31,代码来源:test_vhdl_parser.py

示例4: parse_single_entity

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
 def parse_single_entity(self, code):
     """
     Helper function to parse a single entity
     """
     design_file = VHDLDesignFile.parse(code)
     self.assertEqual(len(design_file.entities), 1)
     return design_file.entities[0]
开发者ID:jonasalowersson,项目名称:vunit,代码行数:9,代码来源:test_vhdl_parser.py

示例5: test_parsing_references

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
    def test_parsing_references(self):
        design_file = VHDLDesignFile.parse(
            """
library name1;
 use name1.foo.all;

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use name1.bla.all;

library lib1,lib2, lib3;
use lib1.foo, lib2.bar,lib3.xyz;

context name1.is_identifier;

entity work1.foo1
entity work1.foo1(a1)
for all : bar use entity work2.foo2
for all : bar use entity work2.foo2 (a2)
for foo : bar use configuration work.cfg

entity foo is -- False
configuration bar of ent -- False

package new_pkg is new lib.pkg;
"""
        )
        self.assertEqual(len(design_file.references), 14)
        self.assertEqual(
            sorted(design_file.references, key=repr),
            sorted(
                [
                    VHDLReference("configuration", "work", "cfg", None),
                    VHDLReference("context", "name1", "is_identifier", None),
                    VHDLReference("entity", "work1", "foo1", "a1"),
                    VHDLReference("entity", "work1", "foo1", None),
                    VHDLReference("entity", "work2", "foo2", "a2"),
                    VHDLReference("entity", "work2", "foo2", None),
                    VHDLReference("package", "ieee", "numeric_std", "all"),
                    VHDLReference("package", "ieee", "std_logic_1164", "all"),
                    VHDLReference("package", "lib1", "foo", None),
                    VHDLReference("package", "lib2", "bar", None),
                    VHDLReference("package", "lib3", "xyz", None),
                    VHDLReference("package", "name1", "bla", "all"),
                    VHDLReference("package", "name1", "foo", "all"),
                    VHDLReference("package", "lib", "pkg", None),
                ],
                key=repr,
            ),
        )
开发者ID:chiggs,项目名称:vunit,代码行数:54,代码来源:test_vhdl_parser.py

示例6: test_getting_architectures_from_design_file

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
    def test_getting_architectures_from_design_file(self):
        design_file = VHDLDesignFile.parse("""
entity foo is
end entity;

architecture rtl of foo is
begin
end architecture;
""")
        self.assertEqual(len(design_file.entities), 1)
        self.assertEqual(len(design_file.architectures), 1)
        arch = design_file.architectures
        self.assertEqual(len(arch), 1)
        self.assertEqual(arch[0].entity, "foo")
        self.assertEqual(arch[0].identifier, "rtl")
开发者ID:jonasalowersson,项目名称:vunit,代码行数:17,代码来源:test_vhdl_parser.py

示例7: test_getting_entities_from_design_file

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
    def test_getting_entities_from_design_file(self):
        design_file = VHDLDesignFile.parse("""
entity entity1 is
end entity;

package package1 is
end package;

entity entity2 is
end entity;
""")
        entities = design_file.entities
        self.assertEqual(len(entities), 2)
        self.assertEqual(entities[0].identifier, "entity1")
        self.assertEqual(entities[1].identifier, "entity2")
开发者ID:jonasalowersson,项目名称:vunit,代码行数:17,代码来源:test_vhdl_parser.py

示例8: test_parsing_references

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
    def test_parsing_references(self):
        design_file = VHDLDesignFile.parse("""
library name1;
 use name1.foo.all;

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use name1.bla.all;

library lib1,lib2, lib3;
use lib1.foo, lib2.bar,lib3.xyz;

context name1.is_identifier;

entity work1.foo1
entity work1.foo1(a1)
for all : bar use entity work2.foo2
for all : bar use entity work2.foo2 (a2)
for foo : bar use configuration work.cfg

entity foo is -- False
configuration bar of ent -- False

package new_pkg is new lib.pkg;
""")
        self.assertEqual(len(design_file.references), 14)
        self.assertEqual(sorted(design_file.references, key=repr), sorted([
            VHDLReference('configuration', 'work', 'cfg', None),
            VHDLReference('context', 'name1', 'is_identifier', None),
            VHDLReference('entity', 'work1', 'foo1', 'a1'),
            VHDLReference('entity', 'work1', 'foo1', None),
            VHDLReference('entity', 'work2', 'foo2', 'a2'),
            VHDLReference('entity', 'work2', 'foo2', None),
            VHDLReference('package', 'ieee', 'numeric_std', 'all'),
            VHDLReference('package', 'ieee', 'std_logic_1164', 'all'),
            VHDLReference('package', 'lib1', 'foo', None),
            VHDLReference('package', 'lib2', 'bar', None),
            VHDLReference('package', 'lib3', 'xyz', None),
            VHDLReference('package', 'name1', 'bla', 'all'),
            VHDLReference('package', 'name1', 'foo', 'all'),
            VHDLReference('package', 'lib', 'pkg', None),
        ], key=repr))
开发者ID:KevinKes,项目名称:vunit,代码行数:46,代码来源:test_vhdl_parser.py

示例9: test_parsing_libraries

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
    def test_parsing_libraries(self):
        design_file = VHDLDesignFile.parse("""
library name1;
 use name1.foo.all;

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use name1.bla.all;

library lib1,lib2, lib3;
use lib1.foo, lib2.bar,lib3.xyz;

context name1.is_identifier;
""")
        self.assertEqual(len(design_file.libraries), 5)
        self.assertEqual(len(design_file.contexts), 0)
        self.assertEqual(design_file.libraries, 
                         {"ieee" : set([("numeric_std", "all"), ("std_logic_1164", "all")]),
                          "name1" : set([("foo", "all"), ("bla", "all"), ("is_identifier",)]),
                          "lib1" : set([("foo",)]),
                          "lib2" : set([("bar",)]),
                          "lib3" : set([("xyz",)])})
开发者ID:tomasnilefrost,项目名称:vunit,代码行数:26,代码来源:test_vhdl_parser.py

示例10: test_parsing_empty

# 需要导入模块: from vunit.vhdl_parser import VHDLDesignFile [as 别名]
# 或者: from vunit.vhdl_parser.VHDLDesignFile import parse [as 别名]
 def test_parsing_empty(self):
     design_file = VHDLDesignFile.parse("")
     self.assertEqual(design_file.entities, [])
     self.assertEqual(design_file.packages, [])
     self.assertEqual(design_file.architectures, [])
开发者ID:jonasalowersson,项目名称:vunit,代码行数:7,代码来源:test_vhdl_parser.py


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