Python Process.write方法代码示例

# 需要导入模块: from vunit.ostools import Process [as 别名]
# 或者: from vunit.ostools.Process import write [as 别名]
    def _create_vsim_process(self):
        """
        Create the vsim process
        """
        ident = threading.current_thread().ident

        with self._lock:
            try:
                vsim_process = self._vsim_processes[ident]
                if vsim_process.is_alive():
                    return vsim_process
            except KeyError:
                pass

            transcript_id = self._transcript_id
            self._transcript_id += 1
            vsim_process = Process([join(self._prefix, "vsim"), "-c",
                                    "-l", join(dirname(self._modelsim_ini), "transcript%i" % transcript_id)])
            self._vsim_processes[ident] = vsim_process

        vsim_process.write("#VUNIT_RETURN\n")

        try:
            consumer = SilentOutputConsumer()
            vsim_process.consume_output(consumer)
        except Process.NonZeroExitCode:
            # Print output if background vsim process startup failed
            LOGGER.error("Failed to start re-usable background vsim process")
            print(consumer.output)
            raise

        return vsim_process

# 需要导入模块: from vunit.ostools import Process [as 别名]
# 或者: from vunit.ostools.Process import write [as 别名]
    def _create_vsim_process(self):
        """
        Create the vsim process
        """
        ident = threading.current_thread().ident

        with self._lock:
            try:
                vsim_process = self._vsim_processes[ident]
                if vsim_process.is_alive():
                    return vsim_process
            except KeyError:
                pass

            transcript_id = self._transcript_id
            self._transcript_id += 1
            vsim_process = Process([
                join(self._prefix, "vsim"), "-c", "-l",
                join(dirname(self._modelsim_ini),
                     "transcript%i" % transcript_id)])
            self._vsim_processes[ident] = vsim_process

        vsim_process.write("#VUNIT_RETURN\n")
        vsim_process.consume_output(silent_output_consumer)
        return vsim_process

# 需要导入模块: from vunit.ostools import Process [as 别名]
# 或者: from vunit.ostools.Process import write [as 别名]
class ModelSimInterface:
    def __init__(self, modelsim_ini="modelsim.ini", persistent=False, gui=False):
        self._modelsim_ini = modelsim_ini

        # Workarround for Microsemi 10.3a which does not 
        # respect MODELSIM environment variable when set within .do script
        # Microsemi bug reference id: dvt64978 
        os.environ["MODELSIM"] = self._modelsim_ini

        self._create_modelsim_ini()
        self._vsim_process = None
        self._gui = gui
        assert not (persistent and gui)

        if persistent:
            self._create_vsim_process()

    def _teardown(self):
        if self._vsim_process is not None:
            self._send_command("quit")
            self._vsim_process.terminate()
            self._vsim_process = None


    def __del__(self):
        self._teardown()

    def _create_vsim_process(self):
        """
        Create the vsim process
        """

        self._vsim_process = Process(["vsim", "-c",
                                      "-l", join(dirname(self._modelsim_ini), "transcript")])
        self._vsim_process.write("#VUNIT_RETURN\n")
        self._vsim_process.consume_output(OutputConsumer(silent=True))

    def _create_modelsim_ini(self):
        if not file_exists(self._modelsim_ini):
            proc = Process(args=['vmap', '-c'], cwd=dirname(self._modelsim_ini))
            proc.consume_output(callback=None)

    def compile_project(self, project, vhdl_standard):
        for library in project.get_libraries():
            self.create_library(library.name, library.directory)

        for source_file in project.get_files_in_compile_order():
            print('Compiling ' + source_file.name + ' ...')

            if source_file.file_type == 'vhdl':
                success = self.compile_vhdl_file(source_file.name, source_file.library.name, vhdl_standard)
            elif source_file.file_type == 'verilog':
                success = self.compile_verilog_file(source_file.name, source_file.library.name)
            else:
                raise RuntimeError("Unkown file type: " + source_file.file_type)

            if not success:
                raise CompileError("Failed to compile '%s'" % source_file.name)
            project.update(source_file)

    def compile_vhdl_file(self, source_file_name, library_name, vhdl_standard):
        try:
            proc = Process(['vcom', '-quiet', '-modelsimini', self._modelsim_ini,
                            '-' + vhdl_standard, '-work', library_name, source_file_name])
            proc.consume_output()
        except Process.NonZeroExitCode:
            return False
        return True

    def compile_verilog_file(self, source_file_name, library_name):
        try:
            proc = Process(['vlog', '-sv', '-quiet', '-modelsimini', self._modelsim_ini,
                            '-work', library_name, source_file_name])
            proc.consume_output()
        except Process.NonZeroExitCode:
            return False
        return True


    _vmap_pattern = re.compile('maps to directory (?P<dir>.*?)\.')
    def create_library(self, library_name, path):

        if not file_exists(dirname(path)):
            os.makedirs(dirname(path))

        if not file_exists(path):
            proc = Process(['vlib', '-unix', path])
            proc.consume_output(callback=None)

        try:
            proc = Process(['vmap', '-modelsimini', self._modelsim_ini, library_name])
            proc.consume_output(callback=None)
        except Process.NonZeroExitCode:
            pass

        match = self._vmap_pattern.search(proc.output)
        if match:
            do_vmap = not file_exists(match.group('dir'))
        else:
            do_vmap = False
#.........这里部分代码省略.........