Python ostools.read_file函数代码示例

    def test_simulate_extra_flags(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
        find_cds_root_irun.return_value = "cds_root_irun"
        find_cds_root_virtuoso.return_value = None
        simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
        config = SimConfig(options={"incisive.irun_sim_flags": ["custom", "flags"]})
        self.assertTrue(simif.simulate("sim_output_path", "lib", "modulename", None, config))
        elaborate_args_file = join("sim_output_path", "irun_elaborate.args")
        simulate_args_file = join("sim_output_path", "irun_simulate.args")
        run_command.assert_has_calls(
            [
                mock.call(
                    [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file)
                ),
                mock.call(
                    [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file)
                ),
            ]
        )

        args = read_file(elaborate_args_file).splitlines()
        self.assertIn("custom", args)
        self.assertIn("flags", args)

        args = read_file(simulate_args_file).splitlines()
        self.assertIn("custom", args)
        self.assertIn("flags", args)

 def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
     check_output.assert_called_once_with(
         [join('prefix', 'irun'), '-f', args_file],
         env=simif.get_env())
     self.assertEqual(read_file(args_file).splitlines(),
                      ['-compile',
                       '-nocopyright',
                       '-licqueue',
                       '-nowarn DLCPTH',
                       '-nowarn DLCVAR',
                       '-v200x -extv200x',
                       '-work work',
                       '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                       '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
                       '-quiet',
                       '-nclibdirname ""',
                       '-makelib lib_path',
                       '"file.vhd"',
                       '-endlib'])

    def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
        find_cds_root_irun.return_value = "cds_root_irun"
        find_cds_root_virtuoso.return_value = None
        simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
        config = make_config(verilog=True)
        self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config, elaborate_only=True))
        elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args')
        run_command.assert_has_calls([
            mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)],
                      cwd=dirname(elaborate_args_file),
                      env=simif.get_env()),
        ])

        self.assertEqual(
            read_file(elaborate_args_file).splitlines(),
            ['-elaborate',
             '-nocopyright',
             '-licqueue',
             '-errormax 10',
             '-nowarn WRMNZD',
             '-nowarn DLCPTH',
             '-nowarn DLCVAR',
             '-ncerror EVBBOL',
             '-ncerror EVBSTR',
             '-ncerror EVBNAT',
             '-work work',
             '-nclibdirname "%s"' % join(self.output_path, "libraries"),
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"),
             '-quiet',
             '-access +r',
             '-input "@run"',
             '-top lib.modulename:sv'])

    def test_simulate_generics_and_parameters(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
        find_cds_root_irun.return_value = "cds_root_irun"
        find_cds_root_virtuoso.return_value = None
        simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
        config = make_config(verilog=True,
                             generics={"genstr": "genval",
                                       "genint": 1,
                                       "genbool": True})
        self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config))
        elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args')
        simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args')
        run_command.assert_has_calls([
            mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)],
                      cwd=dirname(elaborate_args_file),
                      env=simif.get_env()),
            mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)],
                      cwd=dirname(simulate_args_file),
                      env=simif.get_env()),
        ])

        for args_file in [elaborate_args_file, simulate_args_file]:
            args = read_file(args_file).splitlines()
            self.assertIn('-gpg "modulename.genstr => \\"genval\\""', args)
            self.assertIn('-gpg "modulename.genint => 1"', args)
            self.assertIn('-gpg "modulename.genbool => \\"True\\""', args)

 def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
     check_output.assert_called_once_with(
         [join('prefix', 'irun'), '-f', args_file],
         env=simif.get_env())
     self.assertEqual(read_file(args_file).splitlines(),
                      ['-compile',
                       '-nocopyright',
                       '-licqueue',
                       '-nowarn UEXPSC',
                       '-nowarn DLCPTH',
                       '-nowarn DLCVAR',
                       '-work work',
                       '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                       '-hdlvar "custom_hdlvar"',
                       '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
                       '-quiet',
                       '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
                       '-define defname=defval',
                       '-nclibdirname ""',
                       '-makelib lib',
                       '"file.v"',
                       '-endlib'])

def generate_codecs(input_package_design_unit, codec_package_name,  # pylint: disable=too-many-arguments
                    used_packages, output_file, debug):
    """This function generates codecs for the types in the input package and compile the result into
    codec_package_name. used_packages is a list specifying what to include into the result package
    other than the input package. A used package on the format 'lib.pkg' will result in a library and
    a use statement. A used package on the format 'pkg' is assumed to be located in work. output_file
    is where the resulting codec package is written. The debug codecs are generated when debug is set True."""

    # The design unit doesn't contain the package so it must be found first in the source file. This file
    # may contain other packages
    code = read_file(input_package_design_unit.source_file.name)
    package = CodecVHDLPackage.find_named_package(code, input_package_design_unit.name)
    if package is None:
        raise KeyError(input_package_design_unit.name)

    # Get all function declarations and definitions derived from the package type definitions
    declarations, definitions = package.generate_codecs_and_support_functions(debug)

    # Create extra use clauses
    use_clauses = ''
    libraries = []
    for used_package in used_packages if used_packages is not None else []:
        if '.' in used_package:
            if used_package.split('.')[0] not in libraries:
                libraries.append(used_package.split('.')[0])
                use_clauses += 'use %s.all;\n' % used_package
            else:
                use_clauses += 'use work.%s.all;\n' % used_package
    if len(libraries) != 0:
        use_clauses = 'library ' + ';\nlibrary '.join(libraries) + ';\n' + use_clauses

    # Assemble everything and write to output file
    codec_package_template = Template("""\
library vunit_lib;
use vunit_lib.string_ops.all;
context vunit_lib.com_context;

use std.textio.all;

use work.$package_name.all;

$use_clauses
package $codec_package_name is
$declarations
end package $codec_package_name;

package body $codec_package_name is
$definitions
end package body $codec_package_name;

""")

    codec_package = codec_package_template.substitute(
        declarations=declarations,
        definitions=definitions,
        package_name=package.identifier,
        codec_package_name=codec_package_name,
        use_clauses=use_clauses)

    write_file(output_file, codec_package)

    def _preprocess(self, library_name, file_name, preprocessors):
        """
        Preprocess file_name within library_name using explicit preprocessors
        if preprocessors is None then use implicit globally defined processors
        """
        # @TODO dependency checking etc...

        if preprocessors is None:
            preprocessors = [self._location_preprocessor, self._check_preprocessor]
            preprocessors = [p for p in preprocessors if p is not None]
            preprocessors = self._external_preprocessors + preprocessors

        if len(preprocessors) == 0:
            return file_name

        code = ostools.read_file(file_name)
        for preprocessor in preprocessors:
            code = preprocessor.run(code, basename(file_name))

        pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))

        idx = 1
        while ostools.file_exists(pp_file_name):
            LOGGER.debug("Preprocessed file exists '%s', adding prefix", pp_file_name)
            pp_file_name = join(self._preprocessed_path,
                                library_name, "%i_%s" % (idx, basename(file_name)))
            idx += 1

        ostools.write_file(pp_file_name, code)
        return pp_file_name

    def test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_information_is_correct(self):
        licensed_files = []
        for root, _, files in walk(ROOT):
            for file_name in files:
                if 'preprocessed' in root:
                    continue
                if 'codecs' in root:
                    continue
                if root == join(ROOT, "docs"):
                    continue
                osvvm_directory = abspath(join(VHDL_PATH, 'osvvm'))
                if is_prefix_of(osvvm_directory, abspath(join(root, file_name))):
                    continue
                osvvm_integration_example_directory = abspath(
                    join(ROOT, 'examples', 'vhdl', 'osvvm_integration', 'src'))
                if is_prefix_of(osvvm_integration_example_directory, abspath(join(root, file_name))):
                    continue
                if splitext(file_name)[1] in ('.vhd', '.vhdl', '.py', '.v', '.sv'):
                    licensed_files.append(join(root, file_name))

        for file_name in licensed_files:
            code = ostools.read_file(file_name)

            self._check_license(code, file_name)

            if splitext(file_name)[1] in ('.vhd', '.vhdl', '.v', '.sv'):
                self._check_no_trailing_whitespace(code, file_name)

 def __init__(self, name, library, vhdl_parser):
     SourceFile.__init__(self, name, library, 'vhdl')
     self.dependencies = []
     self.depending_components = []
     code = ostools.read_file(self.name)
     self._content_hash = hash_string(code)
     self.parse(code, vhdl_parser)

    def _needs_recompile(self, dependency_graph, source_file):
        """
        Returns True if the source_file needs to be recompiled
        given the dependency_graph, the file contents and the last modification time
        """
        content_hash = source_file.content_hash
        content_hash_file_name = self._hash_file_name_of(source_file)
        if not ostools.file_exists(content_hash_file_name):
            LOGGER.debug("%s has no vunit_hash file at %s and must be recompiled",
                         source_file.name, content_hash_file_name)
            return True

        old_content_hash = ostools.read_file(content_hash_file_name)
        if old_content_hash != content_hash:
            LOGGER.debug("%s has different hash than last time and must be recompiled",
                         source_file.name)
            return True

        for other_file in dependency_graph.get_direct_dependencies(source_file):
            other_content_hash_file_name = self._hash_file_name_of(other_file)

            if not ostools.file_exists(other_content_hash_file_name):
                continue

            if more_recent(other_content_hash_file_name, content_hash_file_name):
                LOGGER.debug("%s has dependency compiled earlier and must be recompiled",
                             source_file.name)
                return True

        LOGGER.debug("%s has same hash file and must not be recompiled",
                     source_file.name)

        return False

 def _create_modelsim_ini(self):
     """
     Create the modelsim.ini file if it does not exist
     """
     if file_exists(self._modelsim_ini):
         return
     write_file(self._modelsim_ini, read_file(join(self._prefix, "..", "modelsim.ini")))

    def _determine_partial_pass(self, output_path):
        """
        In case of simulation failure determine which of the individual test cases failed.
        This is done by reading the test_runner_trace.csv file and checking for test case entry points.
        """
        log_file = join(output_path, "test_runner_trace.csv")

        retval = {}
        for name in self.test_cases:
            retval[name] = FAILED

        if not ostools.file_exists(log_file):
            return retval

        test_log = ostools.read_file(log_file)
        test_starts = []
        for test_name in self._test_cases:
            if "Test Runner,Test case: " + test_name in test_log:
                test_starts.append(test_name)

        for test_name in test_starts[:-1]:
            retval[self._full_name(test_name)] = PASSED

        for test_name in self._test_cases:
            if test_name not in test_starts:
                retval[self._full_name(test_name)] = SKIPPED
        return retval

    def _preprocess(self, library_name, file_name, preprocessors):
        # @TODO dependency checking etc...

        if preprocessors is None:
            preprocessors = [self._location_preprocessor, self._check_preprocessor]
            preprocessors = [p for p in preprocessors if not p is None]
            preprocessors = self._external_preprocessors + preprocessors

        if len(preprocessors) == 0:
            return file_name

        code = ostools.read_file(file_name)
        for p in preprocessors:
            code = p.run(code, basename(file_name))

        pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))

        idx = 1
        while ostools.file_exists(pp_file_name):
            logger.debug("Preprocessed file exists '%s', adding prefix" % pp_file_name)
            pp_file_name = join(self._preprocessed_path,
                                library_name, "%i_%s" % (idx, basename(file_name)))
            idx += 1

        ostools.write_file(pp_file_name, code)
        return pp_file_name

    def _parse(self, entity, architecture_name, verilog):
        """
        Parse file for run strings and pragmas
        """
        scope = create_scope(entity.library_name, entity.name)
        other_file = self._cfg.file_to_scan_for_tests(scope)
        if other_file is not None:
            file_name = other_file
            verilog = file_type_of(other_file) == "verilog"
        elif verilog:
            file_name = entity.file_name
        else:
            file_name = entity.architecture_names[architecture_name]
        code = ostools.read_file(file_name)

        pragmas = self.find_pragmas(code, file_name)

        # @TODO use presence of runner_cfg as tb_filter instead of tb_*
        has_runner_cfg = verilog or ("runner_cfg" in entity.generic_names)

        if has_runner_cfg:
            run_strings = self.find_run_strings(code, file_name, verilog)
        else:
            run_strings = []

        return pragmas, run_strings

 def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
     run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
     self.assertEqual(
         read_file(args_file).splitlines(),
         [
             "-compile",
             "-nocopyright",
             "-licqueue",
             "-nowarn DLCPTH",
             "-nowarn DLCVAR",
             "-v200x -extv200x",
             "-work work",
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
             "-quiet",
             '-nclibdirname ""',
             "-makelib lib_path",
             '"file.vhd"',
             "-endlib",
         ],
     )