Python IncisiveInterface.compile_project方法代码示例

本文整理汇总了Python中vunit.incisive_interface.IncisiveInterface.compile_project方法的典型用法代码示例。如果您正苦于以下问题：Python IncisiveInterface.compile_project方法的具体用法？Python IncisiveInterface.compile_project怎么用？Python IncisiveInterface.compile_project使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类vunit.incisive_interface.IncisiveInterface的用法示例。

在下文中一共展示了IncisiveInterface.compile_project方法的8个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。

示例1: test_compile_project_vhdl_2002

# 需要导入模块: from vunit.incisive_interface import IncisiveInterface [as 别名]
# 或者: from vunit.incisive_interface.IncisiveInterface import compile_project [as 别名]
 def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
     run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
     self.assertEqual(
         read_file(args_file).splitlines(),
         [
             "-compile",
             "-nocopyright",
             "-licqueue",
             "-nowarn DLCPTH",
             "-nowarn DLCVAR",
             "-v200x -extv200x",
             "-work work",
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
             "-quiet",
             '-nclibdirname ""',
             "-makelib lib_path",
             '"file.vhd"',
             "-endlib",
         ],
     )

开发者ID:mark-newsam，项目名称:vunit，代码行数:32，代码来源:test_incisive_interface.py

示例2: test_compile_project_verilog_hdlvar

# 需要导入模块: from vunit.incisive_interface import IncisiveInterface [as 别名]
# 或者: from vunit.incisive_interface.IncisiveInterface import compile_project [as 别名]
 def test_compile_project_verilog_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
     run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
     self.assertEqual(
         read_file(args_file).splitlines(),
         [
             "-compile",
             "-nocopyright",
             "-licqueue",
             "-nowarn UEXPSC",
             "-nowarn DLCPTH",
             "-nowarn DLCVAR",
             "-work work",
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-hdlvar "custom_hdlvar"',
             '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
             "-quiet",
             '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
             "-define defname=defval",
             '-nclibdirname ""',
             "-makelib lib",
             '"file.v"',
             "-endlib",
         ],
     )

开发者ID:mark-newsam，项目名称:vunit，代码行数:35，代码来源:test_incisive_interface.py

示例3: test_compile_project_vhdl_2002

# 需要导入模块: from vunit.incisive_interface import IncisiveInterface [as 别名]
# 或者: from vunit.incisive_interface.IncisiveInterface import compile_project [as 别名]
 def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
     check_output.assert_called_once_with(
         [join('prefix', 'irun'), '-f', args_file],
         env=simif.get_env())
     self.assertEqual(read_file(args_file).splitlines(),
                      ['-compile',
                       '-nocopyright',
                       '-licqueue',
                       '-nowarn DLCPTH',
                       '-nowarn DLCVAR',
                       '-v200x -extv200x',
                       '-work work',
                       '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                       '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
                       '-quiet',
                       '-nclibdirname ""',
                       '-makelib lib_path',
                       '"file.vhd"',
                       '-endlib'])

开发者ID:barri，项目名称:vunit，代码行数:30，代码来源:test_incisive_interface.py

示例4: test_compile_project_verilog_hdlvar

# 需要导入模块: from vunit.incisive_interface import IncisiveInterface [as 别名]
# 或者: from vunit.incisive_interface.IncisiveInterface import compile_project [as 别名]
 def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
     find_cds_root_irun.return_value = "cds_root_irun"
     find_cds_root_virtuoso.return_value = None
     simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
     simif.compile_project(project)
     args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
     check_output.assert_called_once_with(
         [join('prefix', 'irun'), '-f', args_file],
         env=simif.get_env())
     self.assertEqual(read_file(args_file).splitlines(),
                      ['-compile',
                       '-nocopyright',
                       '-licqueue',
                       '-nowarn UEXPSC',
                       '-nowarn DLCPTH',
                       '-nowarn DLCVAR',
                       '-work work',
                       '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                       '-hdlvar "custom_hdlvar"',
                       '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
                       '-quiet',
                       '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
                       '-define defname=defval',
                       '-nclibdirname ""',
                       '-makelib lib',
                       '"file.v"',
                       '-endlib'])

开发者ID:barri，项目名称:vunit，代码行数:33，代码来源:test_incisive_interface.py

示例5: test_compile_project_verilog

# 需要导入模块: from vunit.incisive_interface import IncisiveInterface [as 别名]
# 或者: from vunit.incisive_interface.IncisiveInterface import compile_project [as 别名]
    def test_compile_project_verilog(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
        find_cds_root_irun.return_value = "cds_root_irun"
        find_cds_root_virtuoso.return_value = None
        simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.v", "")
        project.add_source_file("file.v", "lib", file_type="verilog")
        simif.compile_project(project)
        args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
        run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
        self.assertEqual(
            read_file(args_file).splitlines(),
            [
                "-compile",
                "-nocopyright",
                "-licqueue",
                "-nowarn UEXPSC",
                "-nowarn DLCPTH",
                "-nowarn DLCVAR",
                "-work work",
                '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                '-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
                "-quiet",
                '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
                '-nclibdirname ""',
                "-makelib lib",
                '"file.v"',
                "-endlib",
            ],
        )

        self.assertEqual(
            read_file(join(self.output_path, "cds.lib")),
            """\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
"""
            % self.output_path,
        )

开发者ID:mark-newsam，项目名称:vunit，代码行数:47，代码来源:test_incisive_interface.py

示例6: test_compile_project_vhdl_2008

# 需要导入模块: from vunit.incisive_interface import IncisiveInterface [as 别名]
# 或者: from vunit.incisive_interface.IncisiveInterface import compile_project [as 别名]
    def test_compile_project_vhdl_2008(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
        find_cds_root_irun.return_value = "cds_root_irun"
        find_cds_root_virtuoso.return_value = None
        simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.vhd", "")
        project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2008")
        simif.compile_project(project)
        args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
        check_output.assert_called_once_with(
            [join('prefix', 'irun'), '-f', args_file],
            env=simif.get_env())
        self.assertEqual(read_file(args_file).splitlines(),
                         ['-compile',
                          '-nocopyright',
                          '-licqueue',
                          '-nowarn DLCPTH',
                          '-nowarn DLCVAR',
                          '-v200x -extv200x',
                          '-work work',
                          '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                          '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
                          '-quiet',
                          '-nclibdirname ""',
                          '-makelib lib_path',
                          '"file.vhd"',
                          '-endlib'])

        self.assertEqual(read_file(join(self.output_path, "cds.lib")), """\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
""" % self.output_path)

开发者ID:barri，项目名称:vunit，代码行数:40，代码来源:test_incisive_interface.py

示例7: test_simulate_gui

# 需要导入模块: from vunit.incisive_interface import IncisiveInterface [as 别名]
# 或者: from vunit.incisive_interface.IncisiveInterface import compile_project [as 别名]
    def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
        find_cds_root_irun.return_value = "cds_root_irun"
        find_cds_root_virtuoso.return_value = None

        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.vhd", "")
        project.add_source_file("file.vhd", "lib", file_type="vhdl")

        simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, gui=True)
        with mock.patch("vunit.simulator_interface.run_command", autospec=True, return_value=True) as dummy:
            simif.compile_project(project)
        config = SimConfig()
        self.assertTrue(simif.simulate("sim_output_path", "lib", "ent", "arch", config))
        elaborate_args_file = join("sim_output_path", "irun_elaborate.args")
        simulate_args_file = join("sim_output_path", "irun_simulate.args")
        run_command.assert_has_calls(
            [
                mock.call(
                    [join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file)
                ),
                mock.call(
                    [join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file)
                ),
            ]
        )
        self.assertEqual(
            read_file(elaborate_args_file).splitlines(),
            [
                "-elaborate",
                "-nocopyright",
                "-licqueue",
                "-errormax 10",
                "-nowarn WRMNZD",
                "-nowarn DLCPTH",
                "-nowarn DLCVAR",
                "-ncerror EVBBOL",
                "-ncerror EVBSTR",
                "-ncerror EVBNAT",
                "-work work",
                '-nclibdirname "%s"' % join(self.output_path, "libraries"),
                '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                '-log "sim_output_path/irun_elaborate.log"',
                "-quiet",
                '-reflib "lib_path"',
                "-access +rwc",
                "-gui",
                "-top lib.ent:arch",
            ],
        )

        self.assertEqual(
            read_file(simulate_args_file).splitlines(),
            [
                "-nocopyright",
                "-licqueue",
                "-errormax 10",
                "-nowarn WRMNZD",
                "-nowarn DLCPTH",
                "-nowarn DLCVAR",
                "-ncerror EVBBOL",
                "-ncerror EVBSTR",
                "-ncerror EVBNAT",
                "-work work",
                '-nclibdirname "%s"' % join(self.output_path, "libraries"),
                '-cdslib "%s"' % join(self.output_path, "cds.lib"),
                '-log "sim_output_path/irun_simulate.log"',
                "-quiet",
                '-reflib "lib_path"',
                "-access +rwc",
                "-gui",
                "-top lib.ent:arch",
            ],
        )

开发者ID:mark-newsam，项目名称:vunit，代码行数:76，代码来源:test_incisive_interface.py

示例8: test_simulate_gui

# 需要导入模块: from vunit.incisive_interface import IncisiveInterface [as 别名]
# 或者: from vunit.incisive_interface.IncisiveInterface import compile_project [as 别名]
    def test_simulate_gui(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
        find_cds_root_irun.return_value = "cds_root_irun"
        find_cds_root_virtuoso.return_value = None

        project = Project()
        project.add_library("lib", "lib_path")
        write_file("file.vhd", "")
        project.add_source_file("file.vhd", "lib", file_type="vhdl")

        simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, gui=True)
        with mock.patch("vunit.simulator_interface.check_output", autospec=True, return_value="") as dummy:
            simif.compile_project(project)
        config = make_config()
        self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config))
        elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args')
        simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args')
        run_command.assert_has_calls([
            mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)],
                      cwd=dirname(elaborate_args_file),
                      env=simif.get_env()),
            mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)],
                      cwd=dirname(simulate_args_file),
                      env=simif.get_env()),
        ])
        self.assertEqual(
            read_file(elaborate_args_file).splitlines(),
            ['-elaborate',
             '-nocopyright',
             '-licqueue',
             '-errormax 10',
             '-nowarn WRMNZD',
             '-nowarn DLCPTH',
             '-nowarn DLCVAR',
             '-ncerror EVBBOL',
             '-ncerror EVBSTR',
             '-ncerror EVBNAT',
             '-work work',
             '-nclibdirname "%s"' % join(self.output_path, "libraries"),
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"),
             '-quiet',
             '-reflib "lib_path"',
             '-access +rwc',
             '-gui',
             '-top lib.ent:arch'])

        self.assertEqual(
            read_file(simulate_args_file).splitlines(),
            ['-nocopyright',
             '-licqueue',
             '-errormax 10',
             '-nowarn WRMNZD',
             '-nowarn DLCPTH',
             '-nowarn DLCVAR',
             '-ncerror EVBBOL',
             '-ncerror EVBSTR',
             '-ncerror EVBNAT',
             '-work work',
             '-nclibdirname "%s"' % join(self.output_path, "libraries"),
             '-cdslib "%s"' % join(self.output_path, "cds.lib"),
             '-log "%s"' % join("suite_output_path", simif.name, "irun_simulate.log"),
             '-quiet',
             '-reflib "lib_path"',
             '-access +rwc',
             '-gui',
             '-top lib.ent:arch'])

开发者ID:barri，项目名称:vunit，代码行数:68，代码来源:test_incisive_interface.py

注：本文中的vunit.incisive_interface.IncisiveInterface.compile_project方法示例由纯净天空整理自Github/MSDocs等开源代码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。