本文整理汇总了Python中tasks.cvel2函数的典型用法代码示例。如果您正苦于以下问题：Python cvel2函数的具体用法？Python cvel2怎么用？Python cvel2使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了cvel2函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: test1
def test1(self):
'''cvel2 1: Testing default - expected error'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
try:
cvel2()
except Exception:
print 'Expected error!'示例2: test2
def test2(self):
'''cvel2 2: Only input vis set - expected error'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
try:
cvel2(vis = 'myinput.ms')
except Exception:
print 'Expected error!'示例3: test6
def test6(self):
'''cvel2 6: I/O vis set, more complex input vis, one field selected, one spw selected, passall = True'''
if testmms:
return
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
field = '1',
spw = '0',
nchan = 32,
start = 10,
passall = True
)
self.assertNotEqual(rval,False)
# Simulate the passall=True. This MS has fields 0~6
desel = outfile+'.deselected'
split(vis='myinput.ms',outputvis=desel,field='0,2,3,4,5,6',spw='0',datacolumn='all')
mslocal = mstool()
mslocal.open(outfile, nomodify=False)
mslocal.concatenate(msfile=desel)
mslocal.close()
ret = (verify_ms(outfile, 2, 32, 0))
self.assertTrue(ret[0],ret[1])示例4: test41
def test41(self):
'''cvel2 41: test effect of sign of width parameter: optical velocity mode, width positive'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
mytb.open('myinput.ms/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
c = qa.constants('c')['value']
mytb.close()
restf = a[0]
bv1 = c * (restf-a[5])/a[5]
bv2 = c * (restf-a[4])/a[4]
wv = abs(bv2-bv1+1.)
bv2 = bv1 + wv
bv3 = bv2 + wv
a4 = restf/(bv2/c+1.)
a3 = restf/(bv3/c+1.)
b = numpy.array([a3, a4, a[5]])
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode = 'velocity',
veltype = 'optical',
nchan = 3,
start = str(bv1)+'m/s',
width=str(wv)+'m/s',
restfreq=str(restf)+'Hz'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 3, 0, b)
self.assertTrue(ret[0],ret[1])示例5: test14
def test14(self):
'''cvel2 14: I/O vis set, input vis with one spws, one field selected, one spws selected,
passall = False, non-existing phase center...'''
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
try:
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
field = '1',
spw = '0',
passall = False,
mode='frequency',
nchan = 2,
start = '150GHz',
width = '3MHz',
outframe = 'BARY',
phasecenter = 12
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 2, 0)
self.assertTrue(ret[0],ret[1])
except:
print "*** Expected error ***"示例6: test26
def test26(self):
'''cvel2 26: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
lambda0 = 2.99792E8/220398.676E6
lambda1 = 2.99792E8/229586E6
vopt = (lambda1-lambda0)/lambda0 * 2.99792E8
lambda2 = 2.99792E8/(229586E6+1200E3)
vwidth = vopt - (lambda2-lambda0)/lambda0 * 2.99792E8
vopt = vopt-vwidth/2.
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode='velocity',
nchan = 41,
restfreq = '220398.676MHz',
start = str(vopt)+'m/s',
width = str(vwidth)+'m/s',
phasecenter = "J2000 18h25m56.09 -12d04m28.20",
veltype = 'optical'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 41, 0)
self.assertTrue(ret[0],ret[1])示例7: test40
def test40(self):
'''cvel2 40: test effect of sign of width parameter: radio velocity mode, width negative'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
mytb.open('myinput.ms/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
c = qa.constants('c')['value']
mytb.close()
restf = a[0]
bv1 = c * (restf-a[3])/restf
bv2 = c * (restf-a[4])/restf
wv = abs(bv2-bv1)
b = numpy.array([a[3], a[4], a[5]])
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode = 'velocity',
veltype = 'radio',
nchan = 3,
start = str(bv1)+'m/s',
width="-"+str(wv)+'m/s',
restfreq=str(restf)+'Hz'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 3, 0, b)
self.assertTrue(ret[0],ret[1])示例8: test34
def test34(self):
'''cvel2 34: EVLA high-res input MS, 2 spws to combine'''
self.setUp_vis_e()
# os.system('ls -l '+vis_e)
# os.path.exists(vis_e+'/SORTED_TABLE')
#
# # myvis = vis_e
# # os.system('ln -sf ' + myvis + ' myinput.ms')
# rval = cvel2(
# vis = vis_e,
# outputvis = outfile,
# mode = 'velocity',
# restfreq = '6035.092MHz'
# )
# self.assertNotEqual(rval,False)
# ret = verify_ms(outfile, 1, 260, 0)
# self.assertTrue(ret[0],ret[1])
myvis = vis_e
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode = 'velocity',
restfreq = '6035.092MHz'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 260, 0)
self.assertTrue(ret[0],ret[1])示例9: test4
def test4(self):
'''cvel2 4: I/O vis set, more complex input vis, one field selected'''
self.setUp_vis_a()
myvis = vis_a
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis = 'myinput.ms', outputvis = outfile, field = '1')
self.assertNotEqual(rval,False)
ret = (verify_ms(outfile, 1, 64, 0))
self.assertTrue(ret[0],ret[1])示例10: test3
def test3(self):
'''cvel2 3: Input and output vis set'''
self.setUp_vis_b()
myvis = vis_b
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(vis = 'myinput.ms', outputvis = outfile)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 64, 0)
self.assertTrue(ret[0],ret[1])示例11: test53
def test53(self):
'''cvel2 53: cvel2 of a field with ephemeris attached and outframe SOURCE'''
self.setUp_vis_g()
myvis = vis_g
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
outframe = 'SOURCE'
)
self.assertTrue(rval)示例12: test52
def test52(self):
'''cvel2 52: test fftshift regridding: radio velocity mode, width positive'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
# get reference values by running cvel2 with linear interpol
cvel2(
mode = 'velocity',
veltype = 'radio',
restfreq = '220398.676MHz',
vis = 'myinput.ms',
outputvis = outfile,
spw = '0,1',
nchan = 150,
interpolation = 'linear',
outframe = 'CMB'
)
mytb.open(outfile+'/SPECTRAL_WINDOW')
a = mytb.getcell('CHAN_FREQ')
b = numpy.array(a)
mytb.close()
shutil.rmtree(outfile, ignore_errors=True)
rval = cvel2(
mode = 'velocity',
veltype = 'radio',
restfreq = '220398.676MHz',
vis = 'myinput.ms',
outputvis = outfile,
spw = '0,1',
nchan = 150,
interpolation = 'fftshift',
outframe = 'CMB'
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 150, 0, b)
self.assertTrue(ret[0],ret[1])示例13: test27
def test27(self):
'''cvel2 27: SMA input MS, 24 spws to combine, scratch columns, no regridding'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
# no regrid
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 2440, 0)
self.assertTrue(ret[0],ret[1])示例14: test30
def test30(self):
'''cvel2 30: SMA input MS, 24 spws to combine, scratch columns, mode channel_b, no regridding'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode="channel_b"
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 2425, 0)
self.assertTrue(ret[0],ret[1])示例15: test31
def test31(self):
'''cvel2 31: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo'''
self.setUp_vis_d()
myvis = vis_d
os.system('ln -sf ' + myvis + ' myinput.ms')
rval = cvel2(
vis = 'myinput.ms',
outputvis = outfile,
mode="channel",
outframe = "BARY",
phasecenter = "J2000 18h25m56.09 -12d04m28.20"
)
self.assertNotEqual(rval,False)
ret = verify_ms(outfile, 1, 2440, 0)
self.assertTrue(ret[0],ret[1])