本文整理汇总了Python中sst.setProgramOption函数的典型用法代码示例。如果您正苦于以下问题：Python setProgramOption函数的具体用法？Python setProgramOption怎么用？Python setProgramOption使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了setProgramOption函数的12个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: build
def build(root):
paramSets = root.find("param_include")
vars = root.find("variables")
cfg = root.find("config")
timebase = root.find("timebase")
graph = root.find("sst")
if None != vars:
processVars(vars)
if None != paramSets:
processParamSets(paramSets)
if None != timebase:
sst.setProgramOption('timebase', timebase.text.strip())
if None != cfg:
processConfig(cfg)
if None != graph:
buildGraph(graph)示例2: read_arguments
[g_config_file_list, g_overrided_list] = read_arguments()
g_params = setup_config_params(g_config_file_list, g_overrided_list)
if "dumpConfig" in g_params and int(g_params["dumpConfig"]):
print "\n###########################\nDumping global config parameters:"
for key in g_params:
print key + " " + g_params[key]
print "###########################\n"
numChannels = int(g_params["numChannels"])
maxOutstandingReqs = numChannels*64
numTxnPerCycle = numChannels
maxTxns = 100000 * numChannels
# Define SST core options
sst.setProgramOption("timebase", g_params["clockCycle"])
sst.setProgramOption("stopAtCycle", g_params["stopAtCycle"])
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
#########################################################################################################
## Configure transaction generator
comp_txnGen = sst.Component("TxnGen", "CramSim.c_TxnGen")
comp_txnGen.addParams(g_params)
comp_txnGen.addParams({
"maxTxns" : maxTxns,
"numTxnPerCycle" : numTxnPerCycle,
"maxOutstandingReqs" : maxOutstandingReqs,
"readWriteRatio" : 0.5示例3:
# Automatically generated SST Python input
import sst
import os
# Define SST core options
sst.setProgramOption("timebase", "1ps")
sst.setProgramOption("stopAtCycle", "5s")
# Define the simulation components
comp_cpu = sst.Component("cpu", "prospero.prosperoCPU")
comp_cpu.addParams({
"verbose" : "0",
"reader" : "prospero.ProsperoBinaryTraceReader",
"readerParams.file" : "sstprospero-0-0-bin.trace"
})
comp_l1cache = sst.Component("l1cache", "memHierarchy.Cache")
comp_l1cache.addParams({
"access_latency_cycles" : "1",
"cache_frequency" : "2 Ghz",
"replacement_policy" : "lru",
"coherence_protocol" : "MESI",
"associativity" : "8",
"cache_line_size" : "64",
"L1" : "1",
"cache_size" : "64 KB"
})
comp_memory = sst.Component("memory", "memHierarchy.MemController")
comp_memory.addParams({
"coherence_protocol" : "MESI",
"clock" : "1GHz",
"backend.access_time" : "1000 ns",示例4: path
# scheduler simulation input file
import sst
# Define SST core options
sst.setProgramOption("run-mode", "both")
sst.setProgramOption("partitioner", "self")
# Define the simulation components
scheduler = sst.Component("myScheduler", "scheduler.schedComponent")
scheduler.addParams({
"traceName" : "test_scheduler_0003.sim", # job trace path (required)
"scheduler" : "easy", # cons, delayed, easy, elc, pqueue, prioritize. (default: pqueue)
"machine" : "mesh[4,5,2]", # mesh[xdim, ydim, zdim], simple. (default: simple)
"allocator" : "energy", # bestfit, constraint, energy, firstfit, genalg,
# granularmbs, hybrid, mbs, mc1x1, mm, nearest,
# octetmbs, oldmc1x1,random, simple, sortedfreelist.
# (default: simple)
"taskMapper" : "simple", # simple, rcb, random (default: simple)
"FST" : "none", # none, relaxed, strict. (default: none)
"timeperdistance" : ".001865[.1569,0.0129]", # communication overhead params (default: none)
"runningTimeSeed" : "42", # communication overhead randomization seed (default: none)
"dMatrixFile" : "DMatrix4_5_2", # heat recirculation matrix path (default: none)
"coresPerNode" : "1" # default: 1
})
# nodes
n0 = sst.Component("n0", "scheduler.nodeComponent")
n0.addParams({
"nodeNum" : "0",
})
n1 = sst.Component("n1", "scheduler.nodeComponent") 示例5:
import sst
import os
sst.setProgramOption("timebase", "1ps")
sst_root = os.getenv( "SST_ROOT" )
l2PrefetchParams = {
"prefetcher": "cassini.NextBlockPrefetcher"
}
ariel = sst.Component("a0", "ariel.ariel")
ariel.addParams({
"verbose" : "0",
"maxcorequeue" : "256",
"maxissuepercycle" : "2",
"pipetimeout" : "0",
"executable" : sst_root + "/sst/elements/ariel/frontend/simple/examples/stream/stream",
"arielmode" : "1",
"arieltool" : sst_root + "/sst/elements/ariel/fesimple.so",
"memorylevels" : "1",
"defaultlevel" : "0"
})
corecount = 1;
l1cache = sst.Component("l1cache", "memHierarchy.Cache")
l1cache.addParams({
"cache_frequency" : "2 Ghz",
"cache_size" : "64 KB",
"coherence_protocol" : "MSI",示例6:
# scheduler simulation input file
import sst
# Define SST core options
sst.setProgramOption("run-mode", "both")
# Define the simulation components
scheduler = sst.Component("myScheduler", "scheduler.schedComponent")
scheduler.addParams({
"traceName" : "test_scheduler_Atlas.sim",
"machine" : "mesh[4,3,6]",
"coresPerNode" : "8",
"scheduler" : "easy",
"allocator" : "bestfit",
"taskMapper" : "rcb",
"timeperdistance" : ".001865[.1569,0.0129]",
"dMatrixFile" : "none",
"runningTimeSeed" : "42"
})
# nodes
n0 = sst.Component("n0", "scheduler.nodeComponent")
n0.addParams({
"nodeNum" : "0",
})
n1 = sst.Component("n1", "scheduler.nodeComponent")
n1.addParams({
"nodeNum" : "1",
})
n2 = sst.Component("n2", "scheduler.nodeComponent")
n2.addParams({示例7: makeAriel
nextPort += 1
nextAddr += 1
# connect to chain
wrapLink = sst.Link("p%d"%pimNum)
wrapLink.connect((prevRtr,"port0", netLat),
(rtr, "port1", netLat))
sst.popNamePrefix()
return rtr
# "MAIN"
# Define SST core options
sst.setProgramOption("partitioner", "self")
#sst.setProgramOption("stopAtCycle", "2000 us")
#if needed, create the ariel component
if useAriel:
ariel = makeAriel()
#make the CPU
cpuRtr = doCPU()
#make the PIMs
prevRtr = cpuRtr
for x in range(PIMs):
prevRtr = doPIM(x, prevRtr)
# complete the torus示例8:
# Automatically generated SST Python input
import sst
#global system params
g_clockCycle = "1ps"
# Define SST core options
sst.setProgramOption("timebase", g_clockCycle)
sst.setProgramOption("stopAtCycle", "10us")
# Define technology parameters
g_txnParams = {
"numTxnGenReqQEntries":"""50""",
"numTxnGenResQEntries":"""50""",
"numTxnUnitReqQEntries":"""50""",
"numTxnUnitResQEntries":"""50""",
"numTxnDrvBufferQEntries":"""50""",
"relCommandWidth":"""1""",
"numCmdDrvBufferQEntries":"""50""",
"readWriteRatio":"""0.5"""
}
# Define the simulation components
# txn gen
comp_txnGen0 = sst.Component("TxnGen0", "CramSim.c_TxnGenSeq")
comp_txnGen0.addParams(g_txnParams)
# txn driver示例9: MyObject
import sst
from sst.pyproto import *
sst.setProgramOption("stopAtCycle", "10s")
class MyObject(PyProto):
def __init__(self, name):
PyProto.__init__(self, name)
self.name = name
self.countdown = 10
def setActiveLink(self, link):
self.myActiveLink = self.addLink(link, "1us", self._linkHandle)
def _linkHandle(self, event):
print self.name, "LinkHandle %s"%event.type
print self.name, "LinkHandle: ", event.sst
def construct(self):
print self.name, "Construct()"
def init(self, phase):
print self.name, "init(%d)"%phase
def setup(self):
print self.name, "setup()"
def finish(self):示例10: makeAriel
nextAddr += 1
# connect to chain
wrapLink = sst.Link("p%d"%pimNum)
wrapLink.connect((prevRtr,"port0", netLat),
(rtr, "port1", netLat))
sst.popNamePrefix()
return rtr
# "MAIN"
# Define SST core options
#sst.setProgramOption("partitioner", "self")
sst.setProgramOption("stopAtCycle", "300 us")
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
#if needed, create the ariel component
if useAriel:
ariel = makeAriel()
#make the CPU
cpuRtr = doCPU()
#make the PIMs
prevRtr = cpuRtr
for x in range(PIMs):
prevRtr = doPIM(x, prevRtr)
示例11: processConfig
def processConfig(cfg):
for line in cfg.text.strip().splitlines():
var, val = line.split('=')
sst.setProgramOption(var, processString(val)) # strip quotes示例12:
# Automatically generated SST Python input
import sst
import os
# Define SST core options
sst.setProgramOption("timebase", "1ns")
sst.setProgramOption("stopAtCycle", "100000ns")
# Define the simulation components
comp_cpu0 = sst.Component("cpu0", "memHierarchy.trivialCPU")
comp_cpu0.addParams({
"workPerCycle" : """1000""",
"do_write" : """1""",
"commFreq" : """100""",
"memSize" : """0x1000"""
})
comp_c0_l1cache = sst.Component("c0.l1cache", "memHierarchy.Cache")
comp_c0_l1cache.addParams({
"access_latency_cycles" : """2""",
"cache_frequency" : """2 Ghz""",
"replacement_policy" : """lru""",
"coherence_protocol" : """MSI""",
"associativity" : """4""",
"cache_line_size" : """64""",
"cache_size" : """4 KB""",
"printStats" : """1""",
"L1" : """1""",
"debug" : """"""
})
comp_cpu1 = sst.Component("cpu1", "memHierarchy.trivialCPU")
comp_cpu1.addParams({