本文整理汇总了Python中sst.enableAllStatisticsForComponentType函数的典型用法代码示例。如果您正苦于以下问题：Python enableAllStatisticsForComponentType函数的具体用法？Python enableAllStatisticsForComponentType怎么用？Python enableAllStatisticsForComponentType使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了enableAllStatisticsForComponentType函数的5个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1:
#"debug_level" : 10,
"backing" : "none",
"backend.access_time" : "50ns",
"clock" : "1GHz",
"backend.mem_size" : "512MiB",
"memNIC.network_bw" : "50GB/s",
"memNIC.network_address" : 3,
"memNIC.addr_range_start" : 128,
"memNIC.interleave_size" : "128B",
"memNIC.interleave_step" : "256B"
})
# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Scratchpad")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
# Define the simulation links
link_cpu0_l1 = sst.Link("link_cpu0_l1")
link_cpu0_l1.connect( (comp_cpu0, "mem_link", "100ps"), (comp_l1_0, "high_network_0", "100ps") )
link_cpu1_l1 = sst.Link("link_cpu1_l1")
link_cpu1_l1.connect( (comp_cpu1, "mem_link", "100ps"), (comp_l1_1, "high_network_0", "100ps") )
link_l1_l2_0 = sst.Link("link_l1_l2_0")
link_l1_l2_0.connect( (comp_l1_0, "low_network_0", "100ps"), (comp_l2_0, "high_network_0", "100ps") )
link_l1_l2_1 = sst.Link("link_l1_l2_1")
link_l1_l2_1.connect( (comp_l1_1, "low_network_0", "100ps"), (comp_l2_1, "high_network_0", "100ps") )
link_l2_scratch0 = sst.Link("link_cpu0_scratch0")
link_l2_scratch0.connect( (comp_l2_0, "low_network_0", "100ps"), (comp_scratch0, "cpu", "100ps") )
link_l2_scratch1 = sst.Link("link_cpu1_scratch1")示例2:
"debug" : "0"
})
comp_memory = sst.Component("memory", "memHierarchy.MemController")
comp_memory.addParams({
"coherence_protocol" : "MSI",
"debug" : "0",
"backend.mem_size" : "512",
"printStats" : "1",
"clock" : "1GHz",
"backend.access_time" : "100 ns"
})
# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
# Define the simulation links
link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link")
link_cpu0_l1cache_link.connect( (comp_cpu0, "mem_link", "1000ps"), (comp_c0_l1cache, "high_network_0", "1000ps") )
link_c0_l1_l2_link = sst.Link("link_c0_l1_l2_link")
link_c0_l1_l2_link.connect( (comp_c0_l1cache, "low_network_0", "1000ps"), (comp_bus, "high_network_0", "10000ps") )
link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link")
link_cpu1_l1cache_link.connect( (comp_cpu1, "mem_link", "1000ps"), (comp_c1_l1cache, "high_network_0", "1000ps") )
link_c1_l1_l2_link = sst.Link("link_c1_l1_l2_link")
link_c1_l1_l2_link.connect( (comp_c1_l1cache, "low_network_0", "1000ps"), (comp_bus, "high_network_1", "10000ps") )
link_bus_l2cache = sst.Link("link_bus_l2cache")
link_bus_l2cache.connect( (comp_bus, "low_network_0", "10000ps"), (comp_l2cache, "high_network_0", "1000ps") )
link_mem_bus_link = sst.Link("link_mem_bus_link")示例3: xrange
})
ep.addLink(getLink("rtr.%d.%d"%(x-1,y), "ep0.%d.%d"%(x,y)), "rtr", "800ps")
# Add endpoints
for z in xrange(num_endpoints):
rtr.addLink(getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)), "local%d"%(z), "800ps")
if add_no_cut:
getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)).setNoCut()
ep = sst.Component("ep%d.%d.%d"%(z,x,y), "merlin.test_nic")
ep.addParams({
"num_peers" : num_peers,
"link_bw" : "1GB/s",
"linkcontrol_type" : "kingsley.linkcontrol",
"message_size" : msg_size,
"num_messages" : "%d"%(num_messages)
})
ep.addLink(getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)), "rtr", "800ps")
sst.setStatisticLoadLevel(9)
sst.setStatisticOutput("sst.statOutputCSV");
sst.setStatisticOutputOptions({
"filepath" : "stats.csv",
"separator" : ", "
})
sst.enableAllStatisticsForComponentType("kingsley.noc_mesh", {"type":"sst.AccumulatorStatistic","rate":"0ns"})
示例4: int
print "[ %d ] %s" % (x, y)
output = int(raw_input())
if output not in statoutputs:
print "Bad answer. try again."
sys.exit(1)
sst.setStatisticOutput(statoutputs[output]);
if (output != 1):
print "Filename for stats output:"
filename = raw_input()
sst.setStatisticOutputOptions({
"filepath" : filename,
"separator" : ", "
})
endPoint.enableAllStatistics(rate)
topo.prepParams()
endPoint.prepParams()
topo.setEndPoint(endPoint)
topo.build()
if ( stats != 0 ):
sst.enableAllStatisticsForComponentType("merlin.hr_router", {"type":"sst.AccumulatorStatistic",
"rate":rate});
#stats.append("port%d_send_bit_count"%l)
#stats.append("port%d_send_packet_count"%l)
#stats.append("port%d_xbar_stalls"%l)
示例5:
"backend.tCAS" : 3,
"backend.tRCD" : 3,
"backend.tRP" : 3,
"backend.cycle_time" : "5ns",
"backend.row_size" : "8KiB",
"backend.row_policy" : "closed",
"memNIC.network_address" : "2",
"memNIC.network_bw" : "25GB/s",
"memNIC.network_input_buffer_size" : "2KiB",
"memNIC.network_output_buffer_size" : "2KiB",
})
# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
sst.enableAllStatisticsForComponentType("memHierarchy.DirectoryController")
sst.enableAllStatisticsForComponentType("memHierarchy.simpleDRAM")
# Define the simulation links
link_c0_l1cache = sst.Link("link_c0_l1cache")
link_c0_l1cache.connect( (comp_cpu0, "mem_link", "1000ps"), (comp_c0_l1cache, "high_network_0", "1000ps") )
link_c0L1cache_bus = sst.Link("link_c0L1cache_bus")
link_c0L1cache_bus.connect( (comp_c0_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_0", "10000ps") )
link_c1_l1cache = sst.Link("link_c1_l1cache")
link_c1_l1cache.connect( (comp_cpu1, "mem_link", "1000ps"), (comp_c1_l1cache, "high_network_0", "1000ps") )
link_c1L1cache_bus = sst.Link("link_c1L1cache_bus")
link_c1L1cache_bus.connect( (comp_c1_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_1", "10000ps") )
link_bus_n0L2cache = sst.Link("link_bus_n0L2cache")