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Python VerilogParser.parse方法代码示例

本文整理汇总了Python中pyverilog.vparser.parser.VerilogParser.parse方法的典型用法代码示例。如果您正苦于以下问题：Python VerilogParser.parse方法的具体用法？Python VerilogParser.parse怎么用？Python VerilogParser.parse使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类pyverilog.vparser.parser.VerilogParser的用法示例。


在下文中一共展示了VerilogParser.parse方法的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。

示例1: test_bram

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test_bram():
    bram_module = bram.mkTop()
    bram_code = bram_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == bram_code)
开发者ID:hoangt，项目名称:veriloggen，代码行数:14，代码来源:test_bram.py

示例2: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    test_module = submodule_read_verilog_nested.mkTop()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:14，代码来源:test_submodule_read_verilog_nested.py

示例3: test_led

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test_led():
    modules = led.mkThread()
    code = ''.join([ m.to_verilog() for m in modules.values() ])

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:hoangt，项目名称:veriloggen，代码行数:14，代码来源:test_led.py

示例4: test_led

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test_led():
    test_module = instance_noname_args.mkTop()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:14，代码来源:test_instance_noname_args.py

示例5: test_led

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test_led():
    led_module = led.mkLed()
    led_code = led_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == led_code)
开发者ID:hoangt，项目名称:veriloggen，代码行数:14，代码来源:test_led.py

示例6: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    test_module = dataflow_two_outputs_mul.mkTest()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_dataflow_two_outputs_mul.py

示例7: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    modules = from_verilog_pycoram_object.mkUserlogic()
    code = ''.join([ m.to_verilog() for m in modules.values() if not m.used ])

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_from_verilog_pycoram_object.py

示例8: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    test_module = thread_call_from_different_point.mkTest()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_thread_call_from_different_point.py

示例9: test_sort

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test_sort():
    sort_module = sort.mkSimSort()
    sort_code = sort_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator

    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert expected_code == sort_code
开发者ID:hoangt，项目名称:veriloggen，代码行数:15，代码来源:test_sort.py

示例10: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    test_module = regchain.mkRegChain(length=120)
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_regchain.py

示例11: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    test_module = thread_multibank_ram_rtl_connect.mkTest()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_thread_multibank_ram_rtl_connect.py

示例12: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    test_module = seq_delayed_eager_val_lazy_cond.mkTest()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_seq_delayed_eager_val_lazy_cond.py

示例13: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    test_module = from_verilog_module_oldstylecode.mkTop()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_from_verilog_module_oldstylecode.py

示例14: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    test_module = primitive_mux.mkLed()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_primitive_mux.py

示例15: test

# 需要导入模块: from pyverilog.vparser.parser import VerilogParser [as 别名]
# 或者: from pyverilog.vparser.parser.VerilogParser import parse [as 别名]
def test():
    veriloggen.reset()
    test_module = thread_intrinsic_method_prefix.mkTest()
    code = test_module.to_verilog()

    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)

    assert(expected_code == code)
开发者ID:PyHDI，项目名称:veriloggen，代码行数:15，代码来源:test_thread_intrinsic_method_prefix.py


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