Python pyrtl.working_block函数代码示例

 def test_memblock_with_write_enable_with_equalsign(self):
     we = pyrtl.Const(1, bitwidth=1)
     self.output1 <<= self.memory[self.mem_read_address1]
     self.output2 <<= self.memory[self.mem_read_address2]
     self.memory[self.mem_write_address] <<= \
         pyrtl.MemBlock.EnabledWrite(self.mem_write_data, enable=we)
     pyrtl.working_block().sanity_check()

 def test_with_block_exception(self):
     pyrtl.set_working_block(self.block_a)
     with self.assertRaises(pyrtl.PyrtlInternalError):
         with pyrtl.set_working_block(self.block_b):
             self.assertIs(pyrtl.working_block(), self.block_b)
             raise pyrtl.PyrtlInternalError()
     self.assertIs(pyrtl.working_block(), self.block_a)

 def test_unknown_wires(self):
     inp = pyrtl.Input(8, 'inp')
     out = pyrtl.Output(8, 'out')
     out <<= inp
     pyrtl.working_block().wirevector_set.discard(inp)
     with self.assertRaises(pyrtl.PyrtlInternalError):  # sanity_check_net()
         self.sanity_error("Unknown wires")

 def test_async_check_should_pass_with_select(self):
     memory = pyrtl.MemBlock(
                 bitwidth=self.bitwidth, 
                 addrwidth=self.addrwidth-1,
                 name='memory')
     self.output1 <<= memory[self.mem_read_address1[0:-1]]
     pyrtl.working_block().sanity_check()

 def test_memblock_assign_with_extention(self):
     big_output = pyrtl.Output(self.bitwidth+1, "big_output")
     big_output <<= self.memory[self.mem_read_address1]
     self.output1 <<= 1
     self.output2 <<= 2
     self.memory[self.mem_write_address] <<= self.mem_write_data
     pyrtl.working_block().sanity_check()

 def test_async_check_should_pass(self):
     memory = pyrtl.MemBlock(
                 bitwidth=self.bitwidth, 
                 addrwidth=self.addrwidth,
                 name='memory')
     self.output1 <<= memory[self.mem_read_address1]
     memory[self.mem_write_address] <<= self.mem_write_data
     pyrtl.working_block().sanity_check()

 def test_undriven_net(self):
     w = pyrtl.WireVector(name='testwire', bitwidth=3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
     pyrtl.reset_working_block()
     r = pyrtl.Register(3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)
     pyrtl.reset_working_block()
     o = pyrtl.Output(3)
     self.assertRaises(pyrtl.PyrtlError, pyrtl.working_block().sanity_check)

 def test_async_check_should_pass_with_cat(self):
     memory = pyrtl.MemBlock(
                 bitwidth=self.bitwidth, 
                 addrwidth=self.addrwidth,
                 name='memory')
     addr = pyrtl.concat(self.mem_read_address1[0], self.mem_read_address2[0:-1])
     self.output1 <<= memory[addr]
     memory[self.mem_write_address] <<= self.mem_write_data
     pyrtl.working_block().sanity_check()

    def test_const_different_bitwidth_1(self):
        in_w = pyrtl.Input(5)
        const = pyrtl.Const(23, 5)
        const_2 = pyrtl.Const(23, 6)
        wire_1 = in_w + const
        wire_2 = in_w + const_2

        pyrtl.common_subexp_elimination()
        self.num_net_of_type('+', 2)
        pyrtl.working_block().sanity_check()

    def test_const_values_2(self):
        in_w = pyrtl.Input(5)
        const = pyrtl.Const(23, 5)
        const_2 = pyrtl.Const(23, 5)
        wire_1 = in_w + const
        wire_2 = in_w + const_2

        pyrtl.common_subexp_elimination()
        self.num_net_of_type('+', 1)
        pyrtl.working_block().sanity_check()

    def test_2read_1write(self):
        small_memory = pyrtl.MemBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
                                      name='small_memory', max_read_ports=2, max_write_ports=1)
        temp = small_memory[self.mem_read_address1]  # read
        temp2 = small_memory[self.mem_read_address2]  # read

        self.output1 <<= temp
        self.output2 <<= temp2
        small_memory[self.mem_write_address] <<= pyrtl.Const(6)  # write
        pyrtl.working_block().sanity_check()

 def test_valid_slices(self):
     self.valid_slice(8, slice(6))
     self.valid_slice(8, slice(1, 4))
     self.valid_slice(8, slice(1, 8))  # Yes, supplying a end index out of bounds is valid python
     self.valid_slice(8, slice(1, 2, 2))
     self.valid_slice(8, slice(1, 4, 2))
     self.valid_slice(8, slice(7, 1, -2))
     self.valid_slice(8, slice(-2))
     self.valid_slice(8, slice(-6, -2, 3))
     pyrtl.working_block().sanity_check()

 def test_invalid_set_wb(self):
     x = pyrtl.WireVector()
     y = 1
     pyrtl.set_working_block(self.block_a)
     with self.assertRaises(pyrtl.PyrtlError):
         pyrtl.set_working_block(x)
     self.assertEqual(pyrtl.working_block(), self.block_a)
     with self.assertRaises(pyrtl.PyrtlError):
         pyrtl.set_working_block(y)
     self.assertEqual(pyrtl.working_block(), self.block_a)

 def test_with_block_nested(self):
     self.block_c = pyrtl.Block()
     pyrtl.set_working_block(self.block_a)
     self.assertIs(pyrtl.working_block(), self.block_a)
     with pyrtl.set_working_block(self.block_b):
         self.assertIs(pyrtl.working_block(), self.block_b)
         with pyrtl.set_working_block(self.block_c):
             self.assertIs(pyrtl.working_block(), self.block_c)
         self.assertIs(pyrtl.working_block(), self.block_b)
     self.assertIs(pyrtl.working_block(), self.block_a)

 def test_async_check_should_notpass_with_add(self):
     memory = pyrtl.MemBlock(
                 bitwidth=self.bitwidth, 
                 addrwidth=self.addrwidth,
                 name='memory')
     addr = pyrtl.WireVector(self.bitwidth)
     addr <<= self.mem_read_address1 + self.mem_read_address2
     self.output1 <<= memory[addr]
     print(pyrtl.working_block())
     with self.assertRaises(pyrtl.PyrtlError):
         pyrtl.working_block().sanity_check()