Python utils.trim_32函数代码示例

def execute_fmax_s( s, inst ):
  a, b = trim_32( s.fp[inst.rs1] ), trim_32( s.fp[inst.rs2] )
  # TODO: s.fp[ inst.rd ] = sfp.isNaNF32UI(b) || ...
  s.fp[ inst.rd ] = a if sfp.f32_le_quiet(b,a) else b
  s.fcsr          = sfp.get_flags()
  sfp.set_flags( 0 )
  s.pc += 4

def execute_bl( s, inst ):
  if condition_passed( s, inst.cond ):
    s.rf[LR] = trim_32( s.fetch_pc() + 4 )
    offset   = signed( sext_30( inst.imm_24 ) << 2 )
    s.rf[PC] = trim_32( signed( s.rf[PC] ) + offset )
    return
  s.rf[PC] = s.fetch_pc() + 4

def execute_amomax_d( s, inst ):
  addr  = s.rf[inst.rs1]
  value = (( s.mem.read( addr+4, 4 ) << 32 ) \
           | s.mem.read( addr,   4 ))
  new   = max( signed(value, 64), signed(s.rf[inst.rs2], 64) )
  s.mem.write( addr,   4, trim_32( new )       )
  s.mem.write( addr+4, 4, trim_32( new >> 32 ) )
  s.rf[inst.rd] = value
  s.pc += 4

def execute_amoand_d( s, inst ):
  addr  = s.rf[inst.rs1]
  value = (( s.mem.read( addr+4, 4 ) << 32 ) \
           | s.mem.read( addr,   4 ))
  new   = value & s.rf[inst.rs2]
  s.mem.write( addr,   4, trim_32( new )       )
  s.mem.write( addr+4, 4, trim_32( new >> 32 ) )
  s.rf[inst.rd] = value
  s.pc += 4

def execute_sc_d( s, inst ):
  addr = s.rf[inst.rs1]
  if addr == s.load_reservation:
    s.mem.write( addr,   4, trim_32( s.rf[inst.rs2] ) )
    s.mem.write( addr+4, 4, trim_32( s.rf[inst.rs2] >> 32 ) )
    s.rf[inst.rd] = 0
  else:
    s.rf[inst.rd] = 1
  s.pc += 4

def test_execute_arith_shift_right_imm(rn, imm, is16bit):
    rd = 2
    state = new_state(rf0=trim_32(rn))
    instr = (opcode_factory.asr16_immediate(rd=rd, rn=0, imm=imm) if is16bit
             else opcode_factory.asr32_immediate(rd=rd, rn=0, imm=imm))
    name, executefn = decode(instr)
    executefn(state, Instruction(instr, None))
    expected_state = StateChecker(AZ=(False if rn < 0 else True), # 1 >> 5 == 0
                                  AV=0, AC=0,
                                  pc=((2 if is16bit else 4) + RESET_ADDR),
                                  rf2=(trim_32(-1) if rn < 0 else 0))
    expected_state.check(state)

def test_execute_logical_shift_right(rn, rm, is16bit):
    rd = 2
    state = new_state(rf0=trim_32(rn), rf1=trim_32(rm))
    instr = (opcode_factory.lsr16(rd=rd, rn=0, rm=1) if is16bit
             else opcode_factory.lsr32(rd=rd, rn=0, rm=1))
    name, executefn = decode(instr)
    executefn(state, Instruction(instr, None))
    expected_state = StateChecker(AZ=(False if rn < 0 else True), # 1 >> 5 == 0
                                  AV=0, AC=0,
                                  pc=((2 if is16bit else 4) + RESET_ADDR),
                                  rf2=(0b1111 if rn < 0 else 0))
    expected_state.check(state)

def execute_trap16(s, inst):
    """The TRAP instruction causes the processor to halt and wait for external
    inputs. The immediate field within the instruction opcode is not processed
    by the hardware but can be used by software such as a debugger or
    operating system to find out the reason for the TRAP instruction.
    """
    import pydgin.syscalls
    syscall_funcs = {
        2:  pydgin.syscalls.syscall_open,
        3:  pydgin.syscalls.syscall_close,
        4:  pydgin.syscalls.syscall_read,
        5:  pydgin.syscalls.syscall_write,
        6:  pydgin.syscalls.syscall_lseek,
        7:  pydgin.syscalls.syscall_unlink,
        10: pydgin.syscalls.syscall_fstat,
        15: pydgin.syscalls.syscall_stat,
#       19: get_time_of_day,  # TODO r0 = time pointer, r1 = timezone pointer
        21: pydgin.syscalls.syscall_link,
    }
    # Undocumented traps: 0, 1, 2, 6. These are listed as "Reserved" in
    # the reference manual, but have been reported to appear in real programs.
    if inst.t5 == 0 or inst.t5 == 1 or inst.t5 == 2 or inst.t5 == 6:
        if inst.t5 == 0:  # Write.
            syscall_handler = syscall_funcs[5]
        elif inst.t5 == 1:  # Read.
            syscall_handler = syscall_funcs[4]
        elif inst.t5 == 2:  # Open.
            syscall_handler = syscall_funcs[2]
        else:  # Close.
            syscall_handler = syscall_funcs[3]
        retval, errno = syscall_handler(s, s.rf[0], s.rf[1], s.rf[2])
        s.rf[0] = trim_32(retval)
        s.rf[3] = errno
    elif inst.t5 == 3:  # Exit.
        syscall_handler = pydgin.syscalls.syscall_exit
        retval, errno = syscall_handler(s, s.rf[0], s.rf[1], s.rf[2])
    elif inst.t5 == 4:
        if s.debug.enabled('syscalls'):
            print 'TRAP: Assertion SUCCEEDED.'
    elif inst.t5 == 5:
        if s.debug.enabled('syscalls'):
            print 'TRAP: Assertion FAILED.'
    elif inst.t5 == 7: # Initiate system call.
        syscall_handler = syscall_funcs[s.rf[3]]
        retval, errno = syscall_handler(s, s.rf[0], s.rf[1], s.rf[2])
        # Undocumented:
        s.rf[0] = trim_32(retval)
        s.rf[3] = errno
    else:
        print ('WARNING: syscall not implemented: %d. Should be unreachable' %
               inst.t5)
    s.pc += 2

def execute_bic( s, inst ):
  if condition_passed( s, inst.cond ):
    a, (b, cout) = s.rf[ inst.rn ], shifter_operand( s, inst )
    result       = a & trim_32(~b)
    s.rf[ inst.rd ] = trim_32( result )

    if inst.S:
      if inst.rd == 15: raise FatalError('Writing SPSR not implemented!')
      s.N = (result >> 31)&1
      s.Z = trim_32( result ) == 0
      s.C = cout

    if inst.rd == 15:
      return
  s.rf[PC] = s.fetch_pc() + 4

def execute_sbc( s, inst ):
  if condition_passed( s, inst.cond ):
    a, (b, _) = s.rf[ inst.rn ], shifter_operand( s, inst )
    result  = intmask( a - b - (not s.C) )
    s.rf[ inst.rd ] = trim_32( result )

    if inst.S:
      if inst.rd == 15: raise FatalError('Writing SPSR not implemented!')
      s.N = (result >> 31)&1
      s.Z = trim_32( result ) == 0
      s.C = not_borrow_from( result )
      s.V = overflow_from_sub( a, b, result )

    if inst.rd == 15:
      return
  s.rf[PC] = s.fetch_pc() + 4

def execute_mvn( s, inst ):
  if condition_passed( s, inst.cond ):
    a, cout = shifter_operand( s, inst )
    result  = trim_32( ~a )
    s.rf[ inst.rd ] = result

    if inst.S:
      if inst.rd == 15: raise FatalError('Writing SPSR not implemented!')
      s.N = (result >> 31)&1
      s.Z = trim_32( result ) == 0
      s.C = cout
      s.V = s.V

    if inst.rd == 15:
      return
  s.rf[PC] = s.fetch_pc() + 4

 def execute_bcond(s, inst):
     """
     B<COND>:
         IF (Passed)<COND>)) then
         PC = PC + (SignExtend(SIMM) << 1)
     BL:
         LR = next PC;
         PC = PC + (SignExtend(SIMM) << 1)
     """
     if is16bit:
         inst.bits &= 0xFFFF
     cond = inst.cond
     imm = inst.bcond_imm
     if cond == 0 and imm == 0:
         raise RuntimeError(
             (
                 "Epiphany simulator caught infinite loop at runtime. "
                 + "Instruction at pc=%s is attempting to "
                 + "branch unconditionally to itself."
             )
             % hex(s.pc)
         )
     if cond == 0b1111:  # Branch and link (BL).
         s.rf[epiphany.isa.reg_map["LR"]] = s.pc + (2 if is16bit else 4)
     if condition_passed(s, cond):
         offset = (signed(sext_8(imm)) << 1) if is16bit else (signed(sext_24(imm)) << 1)
         s.pc = trim_32(s.pc + offset)
     else:
         s.pc += 2 if is16bit else 4
     s.debug_flags()

def execute_div( s, inst ):
  x    = signed( s.rf[ inst.rs ] )
  y    = signed( s.rf[ inst.rt ] )
  sign = -1 if (x < 0)^(y < 0) else 1

  s.rf[ inst.rd ] = trim_32( abs(x) / abs(y) * sign )
  s.pc += 4

def execute_adc( s, inst ):
  if condition_passed( s, inst.cond ):
    a, (b, _) = s.rf[ inst.rn ], shifter_operand( s, inst )
    result  = a + b + s.C
    s.rf[ inst.rd ] = trim_32( result )

    if inst.S:
      if inst.rd == 15: raise FatalError('Writing SPSR not implemented!')
      s.N = (result >> 31)&1
      s.Z = trim_32( result ) == 0
      s.C = carry_from( result )
      s.V = overflow_from_add( a, b, result )

    if inst.rd == 15:
      return
  s.rf[PC] = s.fetch_pc() + 4

def addressing_mode_2( s, inst ):

  # Immediate vs. Register Offset
  if not inst.I: index    = inst.imm_12
  else:           index, _ = shifter_operand_imm(s, inst)

  Rn          = s.rf[inst.rn]
  offset_addr = Rn + index if inst.U else Rn - index

  # Offset Addressing/Pre-Indexed Addressing vs. Post-Indexed Addressing
  if inst.P: addr = offset_addr
  else:        addr = Rn

  # Offset Addressing vs. Pre-/Post-Indexed Addressing
  if not (inst.P ^ inst.W):
    s.rf[inst.rn] = trim_32( offset_addr )

  return trim_32( addr )