Python test.TestVectorSimulator类代码示例

def run_valrdy_test(dump_vcd, test_verilog, test_vectors, model):

    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):

        model.enq.val.value = test_vector[0]
        model.enq.msg.value = test_vector[2]
        model.deq.rdy.value = test_vector[4]

    def tv_out(model, test_vector):

        assert model.enq.rdy.value == test_vector[1]
        assert model.deq.val.value == test_vector[3]
        if not test_vector[5] == "?":
            assert model.deq.msg.value == test_vector[5]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()

def test_LaneManager_TwoLanes( dump_vcd, test_verilog ):

  # Select and elaborate the model under test

  model = LaneManager( 2 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  data_nbits = 32

  # Define test input and output functions

  def tv_in( model, test_vector ):
    model.from_cpu.val             .value = test_vector[0]
    model.from_cpu.msg[data_nbits:].value = test_vector[1]
    model.from_cpu.msg[:data_nbits].value = test_vector[2]
    model.done[0]                  .value = test_vector[3]
    model.done[1]                  .value = test_vector[4]

  def tv_out( model, test_vector ):
    assert model.from_cpu.rdy == test_vector[5]
    assert model.go           == test_vector[6]
    assert model.size         == test_vector[7]
    assert model.r_baddr      == test_vector[8]
    assert model.v_baddr      == test_vector[9]
    assert model.d_baddr      == test_vector[10]
    assert model.to_cpu       == test_vector[11]

  # Define the test vectors
  test_vectors = [
    # Inputs---------------  Outputs------------------------------------
    # val addr data   dones  rdy go sz rb    vb    db    to_cpu
    [ 0,  1,   0x77,  0, 0,  1,  0, 0, 0x00, 0x00, 0x00, 0 ],
    [ 0,  0,   0x77,  0, 0,  1,  0, 0, 0x00, 0x00, 0x00, 0 ],
    [ 1,  1,   0x08,  0, 0,  1,  0, 0, 0x00, 0x00, 0x00, 0 ],
    [ 1,  1,   0x06,  0, 0,  1,  0, 8, 0x00, 0x00, 0x00, 0 ],
    [ 1,  2,   0x20,  0, 0,  1,  0, 6, 0x00, 0x00, 0x00, 0 ],
    [ 1,  3,   0x30,  0, 0,  1,  0, 6, 0x20, 0x00, 0x00, 0 ],
    [ 1,  4,   0x50,  0, 0,  1,  0, 6, 0x20, 0x30, 0x00, 0 ],
    [ 1,  0,   0x50,  0, 0,  1,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 1,  0,   0x01,  0, 0,  1,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  1, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  1, 0,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 1,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 1,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  0, 6, 0x20, 0x30, 0x50, 1 ],
    [ 0,  0,   0x01,  0, 0,  1,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  1,  0, 6, 0x20, 0x30, 0x50, 0 ],
  ]

  # Create the simulator and configure it
  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )

  # Run the simulator
  sim.run_test()

def run_test_queue( dump_vcd, test_verilog, ModelType, num_entries,
                    test_vectors ):
  """Tests for Multiple Entry Queues."""

  # Instantiate and elaborate the model

  model = ModelType( num_entries, 16 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):

    model.enq.val.value = test_vector[0]
    model.enq.msg.value = test_vector[2]
    model.deq.rdy.value = test_vector[4]

  def tv_out( model, test_vector ):

    assert model.enq.rdy.value   == test_vector[1]
    assert model.deq.val.value   == test_vector[3]
    if not test_vector[5] == '?':
      assert model.deq.msg.value == test_vector[5]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def test_mapper( test_verilog, dump_vcd ):

  a = random.randint(0,0x1ffffffffffff)
  b = random.randint(0,0x1ffffffffffff)
  c = Bits(49,a ^ b)
  d = Bits(49,0)
  for i in xrange(49):
    d += c[i:i+1]

  test_vectors = [
     # in0              in1              out
     [ 0x1ffffffffffff, 0x0000000000000, 0x31],
     [ a,               b,               d   ]
  ]

  model = MapperPRTL()
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  def tv_in( model, test_vector ):
    model.in0.value = test_vector[0]
    model.in1.value = test_vector[1]
  
  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def  test_LeadingOne( test_verilog, dump_vcd ):

   test_vectors = [
      # msg_in            , pos_out , msg_out
      [ 0b0111111111111111, 0b001110, 0b0111111111111111 ],
      [ 0b0000001110000000, 0b001001, 0b0000001110000000 ],
      [ 0b0000010000000000, 0b001010, 0b0000010000000000 ],
      [ 0b0000000000000000, 0b000000, 0b0000000000000000 ],
      [ 0b0000000000001000, 0b000011, 0b0000000000001000 ],
      [ 0b0000110000000010, 0b001001, 0b0000110000000010 ],
   ]

  # Instantiate and elaborate the model

   model = LeadingOne(16,6)
   model.vcd_file = dump_vcd
   if test_verilog:
     model = TranslationTool( model )
   model.elaborate()

  # Define functions mapping the test vector to ports in model

   def tv_in( model, test_vector ):
     model.msg_in.value = test_vector[0]

   def tv_out( model, test_vector ):
     assert model.pos_out.value     == test_vector[1]
     assert model.msg_out.value == test_vector[2]

  # Run the test

   sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
   sim.run_test()

def run_test_mux( dump_vcd, test_verilog,
                  ModelType, num_inputs, test_vectors ):

  # Instantiate and elaborate the model

  model = ModelType(16, num_inputs)
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    for i in range(num_inputs):
      model.in_[i].value = test_vector[i]
    model.sel.value = test_vector[num_inputs]

  def tv_out( model, test_vector ):
    if test_vector[num_inputs] != '?':
      assert model.out.value == test_vector[num_inputs+1]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def test_AdderTree(test_verilog, dump_vcd):

    test_vectors = [
        # in0   in1   in2   out
        [0x01, 0x02, 0x02, 0x05],
        [0x05, 0x02, 0x05, 0x0C],
        [0x00, 0x04, 0x04, 0x08],
        [0x02, 0x03, 0x03, 0x08],
        [0x06, 0x06, 0x06, 0x12],
        [0x07, 0x03, 0x07, 0x11],
        [0x08, 0x08, 0x08, 0x18],
        [0x00, 0x00, 0x00, 0x00],
        [0x32, 0x32, 0x32, 0x96],
        [0x30, 0x31, 0x31, 0x92],
    ]

    model = AdderTree(6, 3)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    def tv_in(model, test_vector):
        model.in_[0].value = test_vector[0]
        model.in_[1].value = test_vector[1]
        model.in_[2].value = test_vector[2]

    def tv_out(model, test_vector):
        if test_vector[3] != "?":
            assert model.out.value == test_vector[3]

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()

def test_basics(dump_vcd):

    # Test vectors

    test_vectors = [
        # in      out
        [0x0000, 0x0001],
        [0x0001, 0x0002],
        [0x000A, 0x000B],
        [0x0401, 0x0402],
        [0xFFFF, 0x0000],
    ]

    # Instantiate and elaborate the model

    model = Incrementer()
    model.vcd_file = dump_vcd
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.in_.value = test_vector[0]

    def tv_out(model, test_vector):
        if test_vector[1] != "?":
            assert model.out == test_vector[1]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()

def run_test_crossbar( model, test_vectors ):

  # Instantiate and elaborate the model

  model.elaborate()

  # Define functions mapping the test vector to ports in model

  num_inputs = len( model.in_ )

  def tv_in( model, test_vector ):
    n = num_inputs
    for i in range(num_inputs):
      model.in_[i].value = test_vector[i]
      model.sel[i].value = test_vector[n+i]

  def tv_out( model, test_vector ):
    n = 2*num_inputs
    for i in range(num_inputs):
      assert model.out[i].value == test_vector[n+i]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def test_FindMax_2( test_verilog, dump_vcd ):

  test_vectors = [
    # in0   in1   out
    [ 0x01, 0x02, 0x02 ],
    [ 0x05, 0x02, 0x05 ],
    [ 0x00, 0x04, 0x04 ],
    [ 0x02, 0x03, 0x03 ],
    [ 0x06, 0x06, 0x06 ],
    [ 0x07, 0x03, 0x07 ],
    [ 0x08, 0x08, 0x08 ],
    [ 0x00, 0x00, 0x00 ],
    [ 0x32, 0x32, 0x32 ],
    [ 0x30, 0x31, 0x31 ],
  ]

  model = FindMax( 6, 2 )
  model.vcd_file = dump_vcd
  if test_verilog:
     model = TranslationTool( model )
  model.elaborate()

  def tv_in( model, test_vector ):
    model.in_[0].value = test_vector[0]
    model.in_[1].value = test_vector[1]

  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def test_FindMaxIdx_3( test_verilog, dump_vcd ):

  test_vectors = [
    # in0   in1   in2   out   idx
    [ 0x01, 0x02, 0x03, 0x03, 0x2 ],
    [ 0x05, 0x02, 0x03, 0x05, 0x0 ],
    [ 0x00, 0x04, 0x03, 0x04, 0x1 ],
    [ 0x02, 0x03, 0x03, 0x03, 0x1 ],
    [ 0x06, 0x06, 0x05, 0x06, 0x0 ],
    [ 0x07, 0x03, 0x07, 0x07, 0x0 ],
    [ 0x08, 0x08, 0x08, 0x08, 0x0 ],
    [ 0x00, 0x00, 0x00, 0x00, 0x0 ],
    [ 0x32, 0x32, 0x32, 0x32, 0x0 ],
    [ 0x30, 0x30, 0x31, 0x31, 0x2 ],
  ]

  model = FindMaxIdx( 6, 3 )
  model.vcd_file = dump_vcd
  if test_verilog:
     model = TranslationTool( model )
  model.elaborate()

  def tv_in( model, test_vector ):
    model.in_[0].value = test_vector[0]
    model.in_[1].value = test_vector[1]
    model.in_[2].value = test_vector[2]

  def tv_out( model, test_vector ):
    if test_vector[3] != '?':
      assert model.out.value == test_vector[3]
    if test_vector[4] != '?':
      assert model.idx.value == test_vector[4]

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def test_adder( test_verilog ):

  # Test vectors

  test_vectors = [
    # in0     in1      out   
    [ 0x0001, 0x0010,  0x0011],
  ]

  # Instantiate and elaborate the model

  model = Adder()
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.in0.value = test_vector[0]
    model.in1.value = test_vector[1]

  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def test_1entry_normal_queue_tv( dump_vcd, test_verilog ):
  '''Single-Element Normal Queue Test Vector Tests

  Directed performance tests for single element queue. We use the
  TestVectorSimulator to do some white box testing.
  '''

  test_vectors = [

    # Enqueue one element and then dequeue it
    # enq.val enq.rdy enq.msg  deq.val deq.rdy deq.msg
    [ 1,      1,      0x0001,  0,      1,      '?'    ],
    [ 0,      0,      0x0000,  1,      1,      0x0001 ],
    [ 0,      1,      0x0000,  0,      0,      '?'    ],

    # Fill in the queue and enq/deq at the same time
    # enq.val enq.rdy enq.msg  deq.val deq.rdy deq.msg
    [ 1,      1,      0x0002,  0,      0,      '?'    ],
    [ 1,      0,      0x0003,  1,      0,      0x0002 ],
    [ 0,      0,      0x0003,  1,      0,      0x0002 ],
    [ 1,      0,      0x0003,  1,      1,      0x0002 ],
    [ 1,      1,      0x0003,  0,      1,      '?'    ],
    [ 1,      0,      0x0004,  1,      1,      0x0003 ],
    [ 1,      1,      0x0004,  0,      1,      '?'    ],
    [ 0,      0,      0x0004,  1,      1,      0x0004 ],
    [ 0,      1,      0x0004,  0,      1,      '?'    ],

  ]

  # Instantiate and elaborate the model

  model = SingleElementNormalQueue( 16 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):

    model.enq.val.value = test_vector[0]
    model.enq.msg.value = test_vector[2]
    model.deq.rdy.value = test_vector[4]

  def tv_out( model, test_vector ):

    assert model.enq.rdy.value   == test_vector[1]
    assert model.deq.val.value   == test_vector[3]
    if not test_vector[5] == '?':
      assert model.deq.msg.value == test_vector[5]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def test_portbundle_bitstruct_param_queue_sim( dump_vcd ):

  test_vectors = [

    # Enqueue one element and then dequeue it
    # enq_val enq_rdy enq_bits deq_val deq_rdy deq_bits
    [ 1,      1,      0x0001,  0,      1,      '?'    ],
    [ 0,      0,      0x0000,  1,      1,      0x0001 ],
    [ 0,      1,      0x0000,  0,      0,      '?'    ],

    # Fill in the queue and enq/deq at the same time
    # enq_val enq_rdy enq_bits deq_val deq_rdy deq_bits
    [ 1,      1,      0x0002,  0,      0,      '?'    ],
    [ 1,      0,      0x0003,  1,      0,      0x0002 ],
    [ 0,      0,      0x0003,  1,      0,      0x0002 ],
    [ 1,      0,      0x0003,  1,      1,      0x0002 ],
    [ 1,      1,      0x0003,  0,      1,      '?'    ],
    [ 1,      0,      0x0004,  1,      1,      0x0003 ],
    [ 1,      1,      0x0004,  0,      1,      '?'    ],
    [ 0,      0,      0x0004,  1,      1,      0x0004 ],
    [ 0,      1,      0x0004,  0,      1,      '?'    ],

  ]

  # Instantiate and elaborate the model

  nports = 4
  model  = ParameterizablePortBundleBitStructQueue( 16, nports )
  model.vcd_file = dump_vcd
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):

    for i in range( nports ):
      model.enq[i].val.v = test_vector[0]
      model.enq[i].msg.v = test_vector[2]
      model.deq[i].rdy.v = test_vector[4]

  def tv_out( model, test_vector ):

    for i in range( nports ):
      assert model.enq[i].rdy.v   == test_vector[1]
      assert model.deq[i].val.v   == test_vector[3]
      if not test_vector[5] == '?':
        assert model.deq[i].msg.v == test_vector[5]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()

def test_regfile_2R2W( dump_vcd, test_verilog ):

  # Test vectors

  test_vectors = [
    # ---read 0---  ---read 1---  -----write 0-----  -----write 1-----
    # addr    data  addr    data  en  addr     data  en  addr     data
    [   10, '?',      14, '?',     0,   10,  0x0000,  0,   10,  0x0000],
    [   13, '?',      14, '?',     1,   14,  0x0005,  0,   14,  0x0005],
    [   12, '?',      14, 0x0005,  0,   10,  0x0006,  1,   12,  0x0006],
    [   12, 0x0006,   12, 0x0006,  0,   13,  0x0008,  1,   13,  0x0009],
    [   12, 0x0006,   12, 0x0006,  0,   13,  0x0007,  0,   13,  0x000a],
    [   17, '?',      13, 0x0009,  0,   17,  0x0090,  1,   17,  0x0010],
    [   14, 0x0005,   17, 0x0010,  0,   17,  0x0090,  0,   17,  0x0020],
    [   16, '?',      17, 0x0010,  1,   17,  0x0090,  1,   16,  0x0090],
    [   16, 0x0090,   17, 0x0090,  1,   17,  0x0011,  0,   16,  0x0011],
    [   16, 0x0090,   17, 0x0011,  0,   10,  0x0000,  0,   10,  0x0000],
  ]

  # Instantiate and elaborate the model

  model = RegisterFile( dtype=16, nregs=32, rd_ports=2, wr_ports=2 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model, verilator_xinit=test_verilog )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.rd_addr[0].value = test_vector[0]
    model.rd_addr[1].value = test_vector[2]
    model.wr_en  [0].value = test_vector[4]
    model.wr_addr[0].value = test_vector[5]
    model.wr_data[0].value = test_vector[6]
    model.wr_en  [1].value = test_vector[7]
    model.wr_addr[1].value = test_vector[8]
    model.wr_data[1].value = test_vector[9]

  def tv_out( model, test_vector ):
    if test_vector[1] != '?':
      assert model.rd_data[0].value == test_vector[1]
    if test_vector[3] != '?':
      assert model.rd_data[1].value == test_vector[3]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()